Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Main Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP0 Tab 4.3.4.4.2. The COMP1 Tab 4.3.4.4.3. The HPS COMP Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The Sys Info 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Info Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Additional Information

3.1. Default Settings

The Agilex™ 5 FPGA E-Series 065B Modular Development Kit ships with its board switches, which are pre-configured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the Factory Default Switch Setting tables to return to its factory settings before proceeding ahead.
Note: X refers to Don't Care in the table below.
Table 4.  Factory Default Switch Settings (Modular Board)
Switch Default Position Function
S4.1 ON
  • ON—MSEL 1 Low
  • OFF—MSEL 1 High
Note: If you want to control the configuration over BTS, set this switch to OFF state.
S4.2 ON
  • ON—MSEL 2 Low
  • OFF—MSEL 2 High
Note: If you want to control the configuration over BTS, set this switch to OFF state.
S1.1 X
  • ON—SWITCH0 (GPIO)
  • OFF—SWITCH0 (GPIO)
S1.2 X
  • ON—SWITCH1 Low
  • OFF—SWITCH1 High
Table 5.  Factory Default Switch Settings (Carrier Board)
Switch Default Position Function
S13.1 OFF
  • ON— PCIe* edge clock
  • OFF—Clock from onboard Si52202
S13.2 OFF
  • ON—USER_DIPSW3 Low
  • OFF—USER_DIPSW3 High
S13.3 OFF
  • ON—EXT header JTAG selected
  • OFF—USB JTAG selected
S13.4 OFF
  • ON—FPGA bypassed from JTAG chain
  • OFF—FPGA Selected
S7.1 OFF
  • ON—USER_DIPSW0 Low
  • OFF—USER_DIPSW0 High
S7.2 OFF
  • ON—USER_DIPSW1 Low
  • OFF—USER_DIPSW1 High
S7.3 OFF
  • ON—USER_DIPSW2 Low
  • OFF—USER_DIPSW2 High
S7.4 ON
  • ON—Disable FMC JTAG mode
  • OFF—Enable FMC JTAG mode
S1.[3:4]

OFF (1)

ON (0)

1PPS_MUX_SEL[1:0]

  • 00—No output at J26 SMA
  • 01—CLK_10M_OUT_SMA at J26
  • 10—TSN_HPS_1PPS_OUT_1V8 at J26
  • 11—TSN_HVIO_1PPS_OUT_1V8 at J26
SW2 POS-1
  • POS-3—ATX 12V input powers the system
  • POS-1— PCIe* EF 12V powers the system
SW4 OFF
  • ON—Enables PCIe* JTAG mode
  • OFF—Enables onboard UBII mode
S5[1:4] ON, OFF, OFF, OFF
PHY 0 CONFIG0:
  • PHY ADDRESS—00000
S2[1:4] OFF, ON, OFF, OFF
PHY 1 CONFIG0:
  • PHY ADDRESS—00001
S6.1 OFF MIPI 0 Vertical Sync (XVS)
  • ON—Enables Signal connection from Agilex™ 5 FPGA device to MIPI0 Module

    OFF—Disable Signal connection from Agilex™ 5 FPGA device to MIPI0 Module

S6.2 OFF MIPI 0 Horizontal Sync (XHS)
  • ON—Enables Signal connection from Agilex™ 5 FPGA device to MIPI0 Module
  • OFF—Disable Signal connection from Agilex™ 5 FPGA device to MIPI0 Module
S6.3 OFF MIPI 0 Trigger (XTRIG)
  • ON—Enables Signal connection from Agilex™ 5 FPGA device to MIPI0 Module
  • OFF—Disable Signal connection from Agilex™ 5 FPGA device to MIPI0 Module
S11.1 OFF MIPI 1 Vertical Sync (XVS)
  • ON—Enables Signal connection from Agilex™ 5 FPGA device to MIPI1 Module
  • OFF—Disable Signal connection from Agilex™ 5 FPGA device to MIPI1 Module
S11.2 OFF MIPI 1 Horizontal Sync (XHS)
  • ON—Enables Signal connection from Agilex™ 5 FPGA device to MIPI1 Module
  • OFF—Disable Signal connection from Agilex™ 5 FPGA device to MIPI1 Module
S11.3 OFF MIPI 1 Trigger (XTRIG)
  • ON—Enables Signal connection from Agilex™ 5 FPGA device to MIPI1 Module
  • OFF—Disable Signal connection from Agilex™ 5 FPGA device to MIPI1 Module
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