Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Main Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP0 Tab 4.3.4.4.2. The COMP1 Tab 4.3.4.4.3. The HPS COMP Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The Sys Info 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Info Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.1.1. Board Components

Table 8.  Board Connector/Switch Description (Modular Board)
Connector/Switch Functionality
J3 Standalone power input
J4 Micro SD card connector
J5 USB Type-C connector
J6 HPS-Ethernet 1G jack
J2 HPS- UART
J9 I2C Header-1
J1 I2C Header-2
J8 I2C Header-3
J7 JTAG
J12 Fan
J10 HPS-Mictor
S4 MSEL switch
S1 GPIO switch
S2 User push button terminated to BW19
S3 Reconfigures the FPGA
S5 Triggers A5E_FPGA_RESET_N_3V3 (BU28)
S6
  • Press for less than 3 seconds: FPGA WARM reset triggered (BP31)
  • Press for more than 3 seconds: A5E_HPS_COLD_NRESET is triggered (CH109/SDMIO10)
S7 HPS PB at IOB_5 (B134)
Table 9.  Board Connector/Switch Description (Carrier Board)
Connector/Switch Functionality
J7 FMC connector
J14 2x3 ATX connector
J4 Dual stacked RJ45
J16 Display Port TX
J15 Display Port RX
J11 HVIO header (2x20)
J23 HVIO header (2x4)
J10 JTAG header (2x5)
J35 Micro USB header
J2 HDMI RX
J3 HDMI TX
J6 SFP28 connector
J19 MIPI0 connector
J20 MIPI1 connector
J9 B2B primary connector
J13 B2B secondary connector
J100 Trisync connector
J5 SDI TX connector
J32 SDI RX connector
J27 I2C VR header
J28 I2C clock header
J33 I2C peripherals header
S1 PPS clock selection switch
S2 TSN PHY 1 configuration control switch
S5 TSN PHY 0 configuration control switch
S6 MIPI0 control signals control switch
S11 MIPI1 control signals control switch
SW2 12 V Input source selection switch
SW4 JTAG input source selection switch
S7 User DIP switch [0:2], FMC JTAG bypass control switch
S13.1 PCIe* reference clock selection switch
S13.2 User DIP switch
S13.3 JTAG source selection switch
S13.4 FPGA JTAG bypass control switch
Level Two Title