Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Main Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP0 Tab 4.3.4.4.2. The COMP1 Tab 4.3.4.4.3. The HPS COMP Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The Sys Info 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Info Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.8. Communication Interfaces

SFP+

The Agilex™ 5 FPGA E-Series 065B Modular Development Kit supports 1x SFP ports. The SFP port fans out from the transceiver channel 1C and port UX3. SFP supports 10G data rate.

TSN/SGMII

The Agilex™ 5 FPGA E-Series 065B Modular Development Kit supports 2x 2.5G TSN over the SGMII interface from the transceiver bank 1C. Ports UX0 and UX1 realize this interface on the Carrier board.

FMC

The Agilex™ 5 FPGA E-Series 065B Modular Development Kit supports 1x FMC+ slot for functional expandability. The x8 FGT lanes from banks 1A and 1B are terminated to FMC J7.

Serial Buses

The Agilex™ 5 FPGA E-Series 065B Modular Development Kit supports 4 major I2C masters from the MAX® 10 BMC.

PMBus

All the voltage regulators with I2C/PMBus support can be accessed through this bus. The bus is shared among the VRs on the Carrier and Modular boards. Over the Modular board, there is a provision to isolate the PMBus from the SDM SVID bus. Refer to I2C tree for further details.

Telemetry

Temperature sensors, current sensors, and EEPROM on the Carrier board are communicated over this bus. This bus is shared with current monitoring, temperature monitoring, power sequences, and reset control components.

This telemetry bus is shared with HPS I2C bus on the Modular board.

Clock

Dedicated bus for all the clock devices supporting I2C on both Modular and Carrier boards.

Table 20.  I2C Debug Headers
Schematic Signal Name Description
PMBUS_SCL_C2M_3V3/SDA PMBus I2C header J9 on the Modular board.
I2C_COM_SCL_C2M_3V3 I2C bus header at J1 on the Modular board.
I2C_SCL2_C2M_3V3/SDA I2C bus header at J8 on Modular board for clock configuration.
PMBUS_SCL_C2M_3V3/SDA PMBus I2C header J27 on the Carrier board.
I2C_SCL2_C2M_B2B_3V3/SDA I2C bus header at J28 on the Carrier board for clock configuration.
I2C_HDMI_DP_SDI_SFP_SCL_3V3/SDA I2C bus header at J33 on the Carrier board for the peripheral device configuration or monitor.
Figure 46. I2C Serial Bus
Level Two Title