Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Main Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP0 Tab 4.3.4.4.2. The COMP1 Tab 4.3.4.4.3. The HPS COMP Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The Sys Info 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Info Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.4. Clocks

Table 10.  Default Clock Frequency (Modular Board)
Schematic Signal Name Default Frequency (MHz) Clock I/O Standard
CLK_A5E_UX_1C_G_100M_DP/DN 100 LVDS Fast 1.8 V
CLK_SDM_REFCLK_125M 125 LVCMOS 1.8 V
CLK_IO96B_3A_DDR4_150M_DP/DN 150 LVDS Fast 1.8 V
CLK_IO96B_2B_DDR4_150M_DP/DN 150 LVDS Fast 1.8 V
CLK_IO96B_3B_DDR4_150M_DP/DN 150 LVDS Fast 1.8 V
CLK_A5E_HVIO_6A_100M 100 LVCMOS 3.3 V
CLK_A5E_HPS_25M_1V8 25 LVCMOS 1.8 V
Table 11.  Carrier Board Clocks
Schematic Signal Name Default Frequency Clock I/O Standard
CLK_SI5518_OUT0_DP 1 Hz LVCMOS 1.8 V
CLK_SI5518_OUT1_1PPS 1 Hz LVCMOS 1.8 V
CLK_1PPS_OUT_SMA 1 Hz LVCMOS 1.8 V
CLK_TOD_156.25M_DP/DN 156.25 MHz LVDS 1.8 V
SI5518_OUT3_DP/DN_MUX_IN — —
CLK_10M_OUT_SMA 10 MHz LVCMOS 1.8V
CLK_SI5518_OUT5_FMC_A_DP/DN — —
CLK_SI5518_OUT6_122.88M_DP/DN 122.88 MHz LVDS 1.8 V
CLK_SI5518_OUT7_156.25M_DP/DN 156.25 MHz LVDS 1.8 V
CLK_SI5518_OUT8_156.25M_DP/DN 156.25 MHz LVDS 1.8 V
CLK_SI5518_OUT9_156.25M_DP/DN 156.25 MHz LVDS 1.8 V
CLK_SI5518_OUT10_156.25M_DP/DN 156.25 MHz LVDS 1.8 V
CLK_SI5518_OUT11_156.25M_DP/DN 156.25 MHz LVDS 1.8 V
CLK_SI5518_OUT12_125M_DP/DN 125 MHz LVDS 1.8 V
FMC_CLK2_C2M_DP/DN 156.25 MHz LVDS 1.8 V
CLK_SI5518_OUT14_100M_DP/DN 100 MHz LVDS 1.8 V
CLK_SI5518_OUT15_100M_DP/DN 100 MHz LVDS 1.8 V
CLK_SI5518_OUT16_100M_DP/DN 100 MHz LVDS 1.8 V
CLK_SI5518_OUT17_150M_DP/DN 150 MHz LVDS 1.8 V

The clocks in the following table are fed to the Modular board transceiver banks from the Carrier board.

Table 12.   Input Clock Sources, Clock Selection Control for Various Modular Board Banks
Pin Name I/O Bank Pin Name ( Agilex™ 5 E-Series FPGA) Signal Connected Carrier Clock Net Clock Source 1 Clock Source 2 Clock Selection Control Default Frequency (MHz)
BB120 1A REFCLK_GTSL1A_CH1p CLK_A5E_UX_1A_R_DP CLK_FMC_GBTCLK1_C_DP FMC Add-in card — — —
BB115 1A REFCLK_GTSL1A_CH1n CLK_A5E_UX_1A_R_DN CLK_FMC_GBTCLK1_C_DN FMC Add-in card — — —
BC111 1A REFCLK_GTSL1A_RX_P CLK_A5E_UX_1A_G_DP CLK_MUX_SI5518_OUT5_SI569_DP CLK(EU13)/OUT5 VCXO CLK (U33) clk_mux_1_sel (EU8) 148.35
BC107 1A REFCLK_GTSL1A_RX_N CLK_A5E_UX_1A_G_DN CLK_MUX_SI5518_OUT5_SI569_DN CLK(EU13)/OUT5 VCXO CLK (U33) clk_mux_1_sel (EU8) 148.35
AV120 1B REFCLK_GTSL1B_CH1p CLK_A5E_UX_1B_R_DP CLK_MUX_SI549_FMC_GBTCLK0_DP VCXO CLK(U34) FMC Add-in card clk_mux_6_sel (EU21) 150
AV115 1B REFCLK_GTSL1B_CH1n CLK_A5E_UX_1B_R_DN CLK_MUX_SI549_FMC_GBTCLK0_DN VCXO CLK(U34) FMC Add-in card clk_mux_6_sel (EU21) 150
AY120 1B REFCLK_GTSL1B_RX_P CLK_A5E_UX_1B_G_DP CLK_MUX_SI5518_OUT6_OUT10_156.25M_DP CLK(EU13)/OUT6 CLK(EU13)/OUT10 clk_mux_3_sel (EU17) 156.25
AY115 1B REFCLK_GTSL1B_RX_N CLK_A5E_UX_1B_G_DN CLK_MUX_SI5518_OUT6_OUT10_156.25M_DN CLK(EU13)/OUT6 CLK(EU13)/OUT10 clk_mux_3_sel (EU17) 156.25
BB16 4A REFCLK_GTSR4A_CH1p CLK_A5E_UX_4A_R_DP CLK_SI549_DISP_PORT_150M_DP VCXO CLK(U32) — — 150
BB21 4A REFCLK_GTSR4A_CH1n CLK_A5E_UX_4A_R_DN CLK_SI549_DISP_PORT_150M_DN VCXO CLK(U32) — — 150
BC29 4A REFCLK_GTSR4A_RX_P CLK_A5E_UX_4A_G_DP CLK_SI5518_OUT17_150M_DP CLK(EU13)/OUT17 — — 150
BC25 4A REFCLK_GTSR4A_RX_N CLK_A5E_UX_4A_G_DN CLK_SI5518_OUT17_150M_DN CLK(EU13)/OUT17 — — 150
AV16 4B REFCLK_GTSR4B_CH1p CLK_A5E_UX_4B_R_DP CLK_HDMI_RX_DP HDMI RETIMER(EU9) — — —
AV21 4B REFCLK_GTSR4B_CH1n CLK_A5E_UX_4B_R_DN CLK_HDMI_RX_DN HDMI RETIMER(EU9) — — —
AY16 4B REFCLK_GTSR4B_RX_P CLK_A5E_UX_4B_G_DP CLK_MUX_SI5518_OUT16_SI569_100M_DP CLK(EU13)/OUT16 VCXO CLK (U1) clk_mux_5_sel (EU5) 100
AY21 4B REFCLK_GTSR4B_RX_N CLK_A5E_UX_4B_G_DN CLK_MUX_SI5518_OUT16_SI569_100M_DN CLK(EU13)/OUT16 VCXO CLK (U1) clk_mux_5_sel (EU5) 100
AP16 4C REFCLK_GTSR4C_CH1p CLK_A5E_UX_4C_R_DP CLK_SI5518_OUT15_100M_DP CLK(EU13)/OUT15 — — 100
AP21 4C REFCLK_GTSR4C_CH1n CLK_A5E_UX_4C_R_DN CLK_SI5518_OUT15_100M_DN CLK(EU13)/OUT15 — — 100
AT16 4C REFCLK_GTSR4C_RX_P CLK_A5E_UX_4C_G_DP CLK_SI53254_OUT0_100M_DP CLK(EU26)/OUT0 — — 100
AT21 4C REFCLK_GTSR4C_RX_N CLK_A5E_UX_4C_G_DN CLK_SI53254_OUT0_100M_DN CLK(EU26)/OUT0 — — 100

When there are input clocks from multiple sources, the clock selection is performed through multiplexers. The following table shows the details of the multiplexers, clock sources, and default clock selected.

Table 13.  Clock Mux Selection
Control Signal

Low

CLOCK0)

High

CLOCK1)

 Output 0 Output 1 Mux Select Default
clk_mux_1_sel CLK_SI5518_OUT5_FMC_A_DP/N CLK_SI569_FMC_A_DP/N CLK_MUX_SI5518_OUT5_SI569_DP/N — High
clk_mux_2_sel CLK_SI5518_OUT7_156.25M_DP/N CLK_SI5518_OUT12_125M_DP/N CLK_MUX_SI5518_OUT9_OUT12_125M_DP/N — High
clk_mux_3_sel CLK_SI5518_OUT6_122.88M_DP/N CLK_SI5518_OUT10_156.25M_DP/N CLK_MUX_SI5518_OUT6_OUT10_156.25M_DP/N — High
clk_mux_4_sel CLK_A5E_1D_REC_DP/N CLK_A5E_1C_REC_DP/N CLK_MUX_A5E_1C_1D_REC_DP/N — High
clk_mux_5_sel CLK_SI5518_OUT16_100M_DP/N CLK_SI569_HDMI_100M_DP_MUX_IN CLK_MUX_SI5518_OUT16_SI569_100M_DP/N REFCLK_4B_DP_MUX_IN Low
clk_mux_6_sel CLK_SI549_FMC_B_DP_MUX_IN FMC_GBTCLK0_M2C_DP/N CLK_MUX_SI549_FMC_GBTCLK0_DP/N CLK_HDMI_1B_100M_DP/N Low
clk_mux_7_sel SI5518_OUT3_DP_MUX_IN REFCLK_4B_DP_MUX_IN CLK_HDMI_4B_100M_DP/N — High

CLK_SI53254_CLKIN_SEL

(S13.1)

CLK_PCIE_EDGE_100M_DP

(from PCIe* Golden Fingers)

CLK_PCIE_100M_DP/DN

(from PCIe* clock generator Si52202)

CLK_SI53254_OUT0_100M_DP/DN CLK_SI53254_OUT1_100M_DP/DN

High

(S13.1 = OFF)
Figure 45. Clock Tree
Level Two Title