Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Main Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP0 Tab 4.3.4.4.2. The COMP1 Tab 4.3.4.4.3. The HPS COMP Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The Sys Info 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Info Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Additional Information

1.2. Feature Summary

  • Agilex™ 5 E-Series A5E065X device in 32 mm x 32 mm, 1591B Package
    • Dual core Arm* Cortex* -A76, Dual core Arm* Cortex* -A55
    • 65K logic elements
    • High-voltage I/O (HVIO)-120 (6 banks)
    • High-speed I/O (HSIO)-384 (IO96B, 4 banks)
    • Low-voltage differential signaling (LVDS)-192 (IO96B)
    • Transceivers-24 (6 banks, 4 lane each)
  • FPGA configuration:
    • 2 Gb flash for Active Serial (AS) x4 configuration mode
    • JTAG header for device programming
    • Built-in Intel® FPGA Download Cable II for device programming
  • Programmable clock sources
  • Transceiver (XCVR) interfaces:
    • 1A: FPGA mezzanine card (FMC) XCVR Lane 4 to Lane 7 (17 Gbps max)
    • 1B: FMC XCVR Lane 0 to Lane 3 (17 Gbps max)
    • 1C:
      • UX0, UX1: 2.5G Time-sensitive networking (TSN)
      • UX2: USB3.1 (on Modular board)
      • UX3: SFP28 (10G)
    • 4A: DisplayPort (DP) 2.0
    • 4B: High-Definition Multimedia Interface (HDMI) 2.1
    • 4C: PCIe* Gen 3/4 x4
      Note: The ES development kit is installed with –6S speed grade FPGA and only supports up to PCIe* Gen 3.0.
  • Memory interfaces:
    • 1x 8GB DDR4-1600 (x32 w/o ECC) for fabric I/O memory on Bank 2B
    • 1x 8GB DDR4-1600 (x32 with ECC) for fabric I/O memory on Bank 3B
    • 1x 8GB DDR4-1600 (x32 with ECC) for HPS processor memory on Bank 3A
  • Other interfaces:
    • IO48 interface for HPS
    • 8 channel MIPI interface to high-speed I/Os (HSIO) bank
  • Mechanical
    • Modular board: 113 mm x 94 mm x 1.6 mm
    • Carrier board: 255 mm x 111 mm x 1.6 mm
    • Active heatsink solution for FPGA
  • Operating environment:
    • Maximum ambient temperature of 0°C–30°C
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