Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Main Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP0 Tab 4.3.4.4.2. The COMP1 Tab 4.3.4.4.3. The HPS COMP Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The Sys Info 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Info Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.5. General Input/Output

Table 14.   MAX® 10 and Modular Board
Schematic Signal Name Description
REMOTE_EN_BMC Enable remote control of GPIOs of the Modular and Carrier boards, i.e., IP switch, push button through soft commands.
SOM_PWR_EN_BMC Enable Modular board power sequencing.
SOM_PWR_OK_M2C_3V3 Power OK indication from Modular board to BMC.
FAN_PWM_C2M_3V3 FAN PWM control for the Modular board active heatsink.
FAN_TACH_C2M_3V3 FAN Tachometer feedback to BMC.
SOM_RESET_C2M_3V3 Mapped to HPS_COLD_RESET on the Modular board.
INIT_DONE_M2C_1V8 Initialization done indication of the Agilex™ 5 E-Series FPGA to BMC.
CONF_DONE_M2C_1V8_BMC Configuration done indication of Agilex™ 5 E-Series FPGA to BMC.
NSTATUS_M2C_1V8 Nstatus Output from Agilex™ 5 E-Series FPGA.
NCONFIG_C2M_1V8 nCONFIG control from BMC to Agilex™ 5 E-Series FPGA.
INT_N_C2M_1V8 Active low interrupt signal generated by MAX® 10 to Agilex™ 5 E-Series FPGA.
SOM_PRSNT_SEC_2 Modular Board Present indication to BMC.
BMC_SPI_CS_3V3 Chip Select signal between Agilex™ 5 E-Series FPGA and BMC (SPI interface).
BMC_SPI_MISO_R_3V3 MISO signal between Agilex™ 5 E-Series FPGA and BMC (SPI interface).
BMC_SPI_MOSI_R_3V3 MOSI signal between Agilex™ 5 E-Series FPGA and BMC (SPI interface).
BMC_SPI_SCLK_3V3 Clock signal between Agilex™ 5 E-Series FPGA and BMC (SPI interface).
Table 15.   MAX® 10 BMC
Schematic Signal Name Description
PG_V1P2_FMC_1V8 Power Good indication of +V1P2.
PG_V1P8_CAR_3V3 Power Good indication of +V1P8.
PG_V1P8_STBY_3V3 Power Good indication of +V1P8_STBY.
PG_V2P5_CAR_3V3 Power Good indication of 2.5 V rail.
PG_V3P3_CAR_1V8 Power Good indication 3.3 V used in the Carrier board.
PG_V3P3_SFP_1V8 Power Good indication SFP28 rail.
BMC_CLK_I2C_SCL BMC I2C Bus SCL for clock devices.
BMC_CLK_I2C_SDA BMC I2C Bus SDA for clock devices.
BMC_SI569_1_FS_3V3_R Si569 Frequency Select (FS) control.
BMC_SI569_3_FS_3V3_R Si569 FS control.
BMC_UART_3V3_FTDI_RXD BMC UART Output to FT4232H chip for UART interface.
BMC_UART_3V3_FTDI_TXD BMC UART input from FT4232H for UART interface.
BMC_UART_RXD_I2C_SCL_3V3 UART RX between BMC and Modular board.
BMC_UART_TXD_I2C_SDA_3V3 UART TX between BMC and Modular board.
CARRIER_PWR_EN_3V3 EN control to Carrier board VRs.
CLK_MUX_1_SEL

SI53307 mux select line control signal.

  • Low—CLK0
  • High—CLK1
CLK_MUX_2_SEL

SI53307 mux select line control signal.

Low—CLK0

High—CLK1
CLK_MUX_3_SEL

SI53307 mux select line control signal.

  • Low—CLK0
  • High—CLK1
CLK_MUX_4_SEL

SI53307 mux select line control signal.

  • Low—CLK0
  • High—CLK1
CLK_MUX_5_SEL

SI53307 mux select line control signal.

  • Low—CLK0
  • High—CLK1
CLK_MUX_6_SEL

SI53307 mux select line control signal.

  • Low—CLK0
  • High—CLK1
CLK_MUX_7_SEL

SI53307 mux select line control signal.

  • Low—CLK0
  • High—CLK1
CLKREQ_PCIE PCIe* CLK REQ signal.
CURR_SNS_CRTCL_3V3 Current sense critical signal from INA3321.
DISP_PORT_TX_CON_CONFIG2_DRIVE_N Display Port TX Config2 Drive signal.
DISP_PORT_TX_CON_CONFIG2_SENSE_N Display Port TX Config Sense signal.
ETH0_INT_N_3V3 Ethernet0 interrupt for Agilex™ 5 D-Series Modular board.
ETH0_RESET_N Ethernet0 reset control signal.
ETH1_INT_N_3V3 Ethernet1 interrupt for Agilex™ 5 D-Series Modular board.
ETH1_RESET_N Ethernet1 reset control signal.
FMC_JTAG_BYPASS FMC JTAG bypass control.
FMC_PG_M2C Power Good indication from FMC card.
FMC_POK_C2M Power Good Indication from BMC to FMC add-on card.
FMC_PRSNT_N FMC card present indication.
FMC_TCK FMC JTAG TCK.
FMC_TDI FMC JTAG TDI.
FMC_TDO FMC JTAG TDO.
FMC_TMS FMC JTAG TMS.
FTDI_RESET_N FTDI reset control.
CARRIER_ADDR1 Carrier Board Revision Bit 1.
CARRIER_ADDR2 Carrier Board Rev Bit 2.
CARRIER_ADDR0 Carrier Board Revision Bit 0.
PG_MDK_BMC Carrier board Power OK Indication (AND of all Power Goods).
I2C_HDMI_DP_SDI_SFP_SCL_3V3 I2C Bus SCL signal for HDMI, SFP, SDI, and DP.
I2C_HDMI_DP_SDI_SFP_SDA_3V3 I2C Bus SDA signal for HDMI, SFP, SDI, and DP.
I2C_LTC4312_EN1 LTC4312 I2C bus control between I2C's from Agilex™ 5 E-Series FPGA (HVIO vs HPS).
I2C_SCL1_C2M_B2B_3V3_HM Clock signal for I2C bus for health monitoring data collection from temp sensor, current sensor.
I2C_SDA1_C2M_B2B_3V3_HM Data signal for I2C bus for health monitoring data collection from temp sensor, current sensor.
JTAG_EXT_PCIE_TCK PCIe* /EXT header JTAG TCK.
JTAG_EXT_PCIE_TDI PCIe* /EXT header JTAG TDI.
JTAG_EXT_PCIE_TDO PCIe* /EXT header JTAG TDO.
JTAG_EXT_PCIE_TDS PCIe* /EXT header JTAG TDS.
JTAG_EXT_PROC_RSTN External JTAG reset indication.
JTAG_EXT_PRSNT# External JTAG present indication.
JTAG_FPGA_BYPASSN Input from SW for JTAG FPGA Bypass.
JTAG_INPUT_SOURCE SW selection for JTAG external or UB-II mode.
JTAG_TCK_C2M_1V8 Modular Board FPGA JTAG TCK signal.
JTAG_TDI_C2M_1V8 Modular Board FPGA JTAG TDI signal.
JTAG_TDO_M2C_1V8 Modular Board FPGA JTAG TDO signal.
JTAG_TMS_C2M_1V8 Modular Board FPGA JTAG TMS signal.
MAX10_CONF_DONE MAX® 10 config done indication signal.
USER_DIPSW3 General-purpose User DIP switch3.
USER_LED_G0 General-purpose user LED0 green.
MAX10_DEV_OE Loss of signal indication from Si53254.
MAX10_JTAG_EN MAX® 10 JTAG Enable pin.
MAX10_NCONFIG MAX® 10 nConfig input signal.
MAX10_NSTATUS MAX® 10 nstatus indication signal.
MIPI_SPI_CS_1V8 Chip Select signal for MIPI interface.
MIPI0_PWR_EN_0_1V8 Drive PWR EN pin of Framos Sensor Module (FSM) High=Normal, Low=Pwr Down (MIPI0 interface related).
MIPI0_RST_0_1V8 General Reset of FSM (MIPI0 interface related).
MIPI1_SPI_CS_1V8 SPI Chip Select signal for Framos1 (MIPI1).
MIPI1_XMASTER0_1V8 Drive XMASTER pin of FSM, MIPI1.
MUX_SEL_JTAG_EXT_USB_R Select between External Dongle or USB JTAG.
OVERTEMP_SHDN_N_3V3

Over temp indication to shutdown all powers.

If triggered "Low", initiate power down sequence.
OVERTEMP_WARN_N_3V3 Over temperature warning.
PCIE_EDGE_SMBCLK_3V3 PCIe* SMBus clock signal.
PCIE_EDGE_SMBDAT_3V3 PCIe* SMBus data.
PG_FRAMOS_3V3 FRAMOS supply Power Good indication.
PG_MPM54304_CAR_IO_1V8 Power Good indication of MPM54304 VR generating non-standby rails.
PG_MPM54304_STBY_RAILS Carrier board standby rails Power Good indication.
PMBUS_SCL_BMC BMC I2C Bus SCL for VRs.
PMBUS_SDA_BMC BMC I2C Bus SDA for VRs.
SEU_ERROR_M2C_1V8 SEU error indication from Modular board to Carrier board.
SFP28_INT_1V8 Active Low interrupt signal generated by MAX® 10 when any of the SFP Control signals change state.
SFP28_LOS_3V3_R SFP28 LOS indication.
SFP28_MOD_DET_3V3_R SFP28 MOD Detect indication.
SFP28_TX_DISABLE_3V3_R SFP28 TX disable control.
SFP28_TX_FAULT_3V3_R SF28 TX fault indication.
SI5518_GPIO0_1V8 Global output from Si5518 (Interrupt).
SI5518_GPIO1_1V8 Output from Si5518, Loss of Lock (LoL) indication.
SI5518_GPIO2_1V8 Global input to Si5518, Output Enable (OE_b).
SI5518_RST_N Reset control input to Si5518.
USER_DIPSW0 General-purpose User DIP switch0.
USER_DIPSW1 General-purpose User DIP switch1.
USER_DIPSW2 General-purpose User DIP switch2.
USER_LED_G1 General-purpose user LED2 green.
USER_LED_R0 General-purpose user LED0 red.
USER_LED_R1 General-purpose user LED1 red.
USER_PB1 User push button switch 1 signal (by default, high).
USER_PB2 User push button switch 2 signal (by default, high).
USER_PB3 User push button switch 3 signal (by default, high).
MSEL0_C2M_1V8 Agilex™ 5 E-Series FPGA configuration Mode Select 0 Signal.
MSEL1_C2M_1V8 Agilex™ 5 E-Series FPGA configuration Mode Select 1 Signal.
MSEL2_C2M_1V8 Agilex™ 5 E-Series FPGA configuration Mode Select 2 Signal.
BMC_JTAG_TMS MAX® 10 JTAG TMS signal.
BMC_JTAG_TCK MAX® 10 JTAG TCK signal.
BMC_JTAG_TDI MAX® 10 JTAG TDI signal.
BMC_JTAG_TDO MAX® 10 JTAG TDO signal.
MIPI1_RST_0_1V8 General reset of FSM (MIPI1 interface related).
MIPI1_PWR_EN_0_1V8 Drive PWR EN pin of FSM High=Normal, Low=Pwr Down (MIPI1 interface related).
MIPI0_XMASTER0_1V8 Drive XMASTER Pin of FSM, MIPI0.
MIPI0_SPI_CS_1V8 SPI Chip Select signal for Framos0 (MIPI0).
WAKE_PCIE PCIe* wake signal.
Level Two Title