Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

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ID 820977
Date 7/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. HPS Boot 8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash U24 with Default Factory Image 3.3.2. Restoring SD Card with the Default Factory Image
4. Board Test System x
4.1. Setting Up BTS GUI Running Environment 4.2. Troubleshooting for Launching BTS 4.3. BTS Functionalities
4.1. Setting Up BTS GUI Running Environment x
4.1.1. Installing Quartus® Prime Software 4.1.2. Running the BTS GUI
4.3. BTS Functionalities x
4.3.1. The Clock Functionality 4.3.2. The Power Functionality 4.3.3. The MAX® 10 Functionality 4.3.4. Agilex™ 5 FPGA Functionality 4.3.5. Other Functionalities
4.3.1. The Clock Functionality x
4.3.1.1. Si5332 4.3.1.2. Si5518 4.3.1.3. Si549 4.3.1.4. Si569 4.3.1.5. Si52202
4.3.2. The Power Functionality x
4.3.2.1. Power Monitor 4.3.2.2. Temperature Monitor
4.3.3. The MAX® 10 Functionality x
4.3.3.1. The System Tab 4.3.3.2. The IO Control Tab
4.3.4. Agilex™ 5 FPGA Functionality x
4.3.4.1. The Configure Menu 4.3.4.2. The Main Info Tab 4.3.4.3. The Transceiver Tab 4.3.4.4. The Memory Tab
4.3.4.3. The Transceiver Tab x
4.3.4.3.1. The FMC+ Tab 4.3.4.3.2. The SFP+ Tab
4.3.4.3.1. The FMC+ Tab x
4.3.4.3.1.1. The FMC+ Test Tab 4.3.4.3.1.2. The FMC+ Status Tab
4.3.4.4. The Memory Tab x
4.3.4.4.1. The COMP0 Tab 4.3.4.4.2. The COMP1 Tab 4.3.4.4.3. The HPS COMP Tab
4.3.5. Other Functionalities x
4.3.5.1. The Diagnostic Functionality 4.3.5.2. The Sys Info 4.3.5.3. The Connection Information 4.3.5.4. The Bottom Info Bar
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device by Active Serial (AS) Modes (Default Mode)
6. Custom Projects for the Development Kit x
6.1. Golden Top 6.2. EMIF Pin Swizzling Setting
A. Development Kit Components x
A.1. Board Overview A.2. System Management A.3. Power A.4. Clocks A.5. General Input/Output A.6. Memory Interfaces A.7. Board to Board Connector A.8. Communication Interfaces
A.1. Board Overview x
A.1.1. Board Components
A.7. Board to Board Connector x
A.7.1. Modular Board Primary Connector A.7.2. Modular Board Secondary Connector A.7.3. Carrier Board Primary Connector A.7.4. Carrier Board Secondary Connector
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. HPS Boot
8. Document Revision History for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.7.2. Modular Board Secondary Connector

Table 17.  Modular Board Secondary Connector (J13)
  A B C D
1 SOM_PRSNT_SEC_1 +V_HVIO_6CD_C2M GND +V_HVIO_6EF_C2M
2 GND A5E_HVIO_6D_17 GND A5E_HVIO_6D_14
3 A5E_HVIO_6D_11 A5E_HVIO_6D_15 A5E_HVIO_6D_18 A5E_HVIO_6D_19
4 A5E_HVIO_6D_16 GND A5E_HVIO_6D_13 GND
5 A5E_HVIO_6D_20 A5E_HVIO_6D_12 A5E_HVIO_6D_10 A5E_HVIO_6D_7
6 GND A5E_HVIO_6D_8 GND A5E_HVIO_6D_2
7 A5E_HVIO_6D_5 A5E_HVIO_6D_9 A5E_HVIO_6D_6 A5E_HVIO_6D_4
8 A5E_HVIO_6D_3 GND A5E_HVIO_6D_1 GND
9 A5E_HVIO_6C_6 A5E_HVIO_6C_5 A5E_HVIO_6C_13 A5E_HVIO_6C_17
10 GND A5E_HVIO_6C_7 GND A5E_HVIO_6C_1
11 A5E_HVIO_6C_8 A5E_HVIO_6C_4 A5E_HVIO_6C_3 A5E_HVIO_6C_18
12 A5E_HVIO_6C_11 GND A5E_HVIO_6C_20 GND
13 A5E_HVIO_6C_12 A5E_HVIO_6C_9 A5E_HVIO_6C_2 A5E_HVIO_6C_19
14 GND A5E_HVIO_6C_14 GND A5E_HVIO_6C_10
15 A5E_HVIO_6C_16 A5E_HVIO_6C_15 A5E_HVIO_6E_12 A5E_HVIO_6E_10
16 A5E_HVIO_6E_18 GND A5E_HVIO_6E_1 GND
17 A5E_HVIO_6E_17 A5E_HVIO_6E_14 A5E_HVIO_6E_13 A5E_HVIO_6E_15
18 GND A5E_HVIO_6E_19 GND A5E_HVIO_6E_20
19 A5E_HVIO_6E_7 A5E_HVIO_6E_4 A5E_HVIO_6E_2 A5E_HVIO_6E_11
20 A5E_HVIO_6E_5 GND A5E_HVIO_6E_3 GND
21 A5E_HVIO_6E_6 A5E_HVIO_6E_8 A5E_HVIO_6E_9 A5E_HVIO_6E_16
22 GND A5E_HVIO_6F_20 GND A5E_HVIO_6F_16
23 A5E_HVIO_6F_18 A5E_HVIO_6F_19 A5E_HVIO_6F_15 A5E_HVIO_6F_17
24 A5E_HVIO_6F_14 GND A5E_HVIO_6F_13 GND
25 A5E_HVIO_6F_12 A5E_HVIO_6F_11 A5E_HVIO_6F_10 A5E_HVIO_6F_9
26 GND A5E_HVIO_6F_8 GND A5E_HVIO_6F_4
27 A5E_HVIO_6F_3 A5E_HVIO_6F_7 A5E_HVIO_6F_1 A5E_HVIO_6F_2
28 A5E_HVIO_6F_5 GND A5E_HVIO_6F_6 GND
29 GND A5E_UX_4C_RX3_DN GND A5E_UX_4C_RX2_DN
30 GND A5E_UX_4C_RX3_DP GND A5E_UX_4C_RX2_DP
31 A5E_UX_4C_TX3_DN GND A5E_UX_4C_TX2_DN GND
32 A5E_UX_4C_TX3_DP GND A5E_UX_4C_TX2_DP GND
33 GND A5E_UX_4C_RX1_DN GND A5E_UX_4C_RX0_DN
34 GND A5E_UX_4C_RX1_DP GND A5E_UX_4C_RX0_DP
35 A5E_UX_4C_TX1_DN GND A5E_UX_4C_TX0_DN GND
36 A5E_UX_4C_TX1_DP GND A5E_UX_4C_TX0_DP GND
37 GND CLK_A5E_UX_4C_R_DN GND CLK_A5E_UX_4C_G_DN
38 GND CLK_A5E_UX_4C_R_DP GND CLK_A5E_UX_4C_G_DP
39 A5E_UX_4D_RX3_DN GND A5E_UX_4D_RX2_DN GND
40 A5E_UX_4D_RX3_DP GND A5E_UX_4D_RX2_DP GND
41 GND A5E_UX_4D_TX3_DN GND A5E_UX_4D_TX2_DN
42 GND A5E_UX_4D_TX3_DP GND A5E_UX_4D_TX2_DP
43 A5E_UX_4D_RX1_DN GND A5E_UX_4D_RX0_DN GND
44 A5E_UX_4D_RX1_DP GND A5E_UX_4D_RX0_DP GND
45 GND A5E_UX_4D_TX1_DN GND A5E_UX_4D_TX0_DN
46 GND A5E_UX_4D_TX1_DP GND A5E_UX_4D_TX0_DP
47 NC GND NC GND
48 NC GND NC GND
49 GND A5E_UX_4B_RX3_DN GND A5E_UX_4B_RX2_DN
50 GND A5E_UX_4B_RX3_DP GND A5E_UX_4B_RX2_DP
51 A5E_UX_4B_TX3_DN GND A5E_UX_4B_TX2_DN GND
52 A5E_UX_4B_TX3_DP GND A5E_UX_4B_TX2_DP GND
53 GND A5E_UX_4B_RX1_DN GND A5E_UX_4B_RX0_DN
54 GND A5E_UX_4B_RX1_DP GND A5E_UX_4B_RX0_DP
55 A5E_UX_4B_TX1_DN GND A5E_UX_4B_TX0_DN GND
56 A5E_UX_4B_TX1_DP GND A5E_UX_4B_TX0_DP GND
57 GND CLK_A5E_UX_4B_R_DN GND CLK_A5E_UX_4B_G_DN
58 GND CLK_A5E_UX_4B_R_DP GND CLK_A5E_UX_4B_G_DP
59 A5E_UX_4A_RX3_DN GND A5E_UX_4A_RX2_DN GND
60 A5E_UX_4A_RX3_DP GND A5E_UX_4A_RX2_DP GND
61 GND A5E_UX_4A_TX3_DN GND A5E_UX_4A_TX2_DN
62 GND A5E_UX_4A_TX3_DP GND A5E_UX_4A_TX2_DP
63 A5E_UX_4A_RX1_DN GND A5E_UX_4A_RX0_DN GND
64 A5E_UX_4A_RX1_DP GND A5E_UX_4A_RX0_DP GND
65 GND A5E_UX_4A_TX1_DN GND A5E_UX_4A_TX0_DN
66 GND A5E_UX_4A_TX1_DP GND A5E_UX_4A_TX0_DP
67 CLK_A5E_UX_4A_R_DN GND CLK_A5E_UX_4A_G_DN GND
68 CLK_A5E_UX_4A_R_DP GND CLK_A5E_UX_4A_G_DP GND
69 GND A5E_HVIO_6G_14 GND A5E_HVIO_6G_17
70 A5E_HVIO_6G_13 A5E_HVIO_6G_10 A5E_HVIO_6G_16 A5E_HVIO_6G_11
71 A5E_HVIO_6G_2 GND A5E_HVIO_6G_19 GND
72 A5E_HVIO_6G_5 A5E_HVIO_6G_1 A5E_HVIO_6G_8 A5E_HVIO_6G_15
73 GND A5E_HVIO_6G_7 GND A5E_HVIO_6G_20
74 A5E_HVIO_6G_4 A5E_HVIO_6G_6 A5E_HVIO_6G_9 A5E_HVIO_6G_18
75 A5E_HVIO_6G_3 GND A5E_HVIO_6G_12 GND
76 A5E_HVIO_6H_18 A5E_HVIO_6H_17 A5E_HVIO_6H_3 A5E_HVIO_6H_5
77 GND A5E_HVIO_6H_2 GND A5E_HVIO_6H_6
78 A5E_HVIO_6H_7 A5E_HVIO_6H_11 A5E_HVIO_6H_12 A5E_HVIO_6H_4
79 A5E_HVIO_6H_20 GND A5E_HVIO_6H_15 GND
80 A5E_HVIO_6H_19 A5E_HVIO_6H_8 A5E_HVIO_6H_16 A5E_HVIO_6H_1
81 GND A5E_HVIO_6H_14 GND A5E_HVIO_6H_13
82 A5E_HVIO_6H_10 A5E_HVIO_6H_9 NC NC
83 NC GND NC GND
84 NC NC NC A5E_4C_PERSTN_HVIO_6A_7_3V3
85 GND NC GND NC
86 NC NC A5E_HPS_1PPS_OUT A5E_HVIO_6A_20_3V3
87 NC GND A5E_HPS_1PPS_IN GND
88 NC NC NC NC
89 GND A5E_HVIO_6B_17 GND A5E_HVIO_6B_18
90 A5E_HVIO_6B_14 A5E_HVIO_6B_19 A5E_HVIO_6B_16 A5E_HVIO_6B_20
91 A5E_HVIO_6B_10 GND A5E_HVIO_6B_11 GND
92 A5E_HVIO_6B_13 A5E_HVIO_6B_2 A5E_HVIO_6B_1 A5E_HVIO_6B_15
93 GND A5E_HVIO_6B_8 GND A5E_HVIO_6B_12
94 A5E_HVIO_6B_5 A5E_HVIO_6B_7 A5E_HVIO_6B_6 A5E_HVIO_6B_4
95 A5E_HVIO_6B_3 GND A5E_HVIO_6B_9 GND
96 GND +V_HVIO_6B_C2M GND +V_HVIO_6GH_C2M
97 GND GND GND SOM_PRSNT_SEC_2
98 +V12P0 +V12P0 +V12P0 +V12P0
99 GND GND GND GND
100 +V12P0 +V12P0 +V12P0 +V12P0
Level Two Title