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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem
3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank
3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane
3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree
3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree
3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks
3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment
3.2.9. User Clock in Different Core Access Modes
6.2.3.1. Address and Command Pin Placement for DDR4
6.2.3.2. DDR4 Data Width Mapping
6.2.3.3. General Guidelines
6.2.3.4. x4 DIMM Implementation
6.2.3.5. Specific Pin Connection Requirements
PLL
OCT
Address and Command
DQS/DQ/DM
6.2.3.6. Command and Address Signals
6.2.3.7. Clock Signals
6.2.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology
6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology
6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology
6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations
6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations
6.4.3.6. DDR4 Simulation Strategy
12.1. Interface Configuration Performance Issues
12.2. Functional Issue Evaluation
12.3. Timing Issue Characteristics
12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
12.5. Debugging with the External Memory Interface Debug Toolkit
12.6. Generating Traffic with the Test Engine IP
12.7. Guidelines for Developing HDL for Traffic Generator
12.8. Guidelines for Traffic Generator Status Check
12.9. Hardware Debugging Guidelines
12.10. Create a Simplified Design that Demonstrates the Same Issue
12.11. Measure Power Distribution Network
12.12. Measure Signal Integrity and Setup and Hold Margin
12.13. Vary Voltage
12.14. Operate at a Lower Speed
12.15. Determine Whether the Issue Exists in Previous Versions of Software
12.16. Determine Whether the Issue Exists in the Current Version of Software
12.17. Try A Different PCB
12.18. Try Other Configurations
12.19. Debugging Checklist
12.20. Categorizing Hardware Issues
12.21. Signal Integrity Issues
12.22. Characteristics of Signal Integrity Issues
12.23. Evaluating Signal Integrity Issues
12.24. Skew
12.25. Crosstalk
12.26. Power System
12.27. Clock Signals
12.28. Address and Command Signals
12.29. Read Data Valid Window and Eye Diagram
12.30. Write Data Valid Window and Eye Diagram
12.31. Hardware and Calibration Issues
12.32. Memory Timing Parameter Evaluation
12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
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6.2.3.5. Specific Pin Connection Requirements
PLL
- You must constrain the PLL reference clock to the address and command sub-bank only.
- You must constrain differential reference clocks to pin indices 0 and 1 in lane AC2.
- The sharing of PLL reference clocks across multiple interfaces is permitted; however, pin indices 0 and 1 of lane 2 of the address and command sub-bank for all slave EMIF interfaces can be used only for supplying reference clocks. Altera recommends that you consider connecting these clock input pins to a reference clock source to facilitate greater system implementation flexibility.
Note: Agilex™ 5 FPGAs do not support single-ended I/O PLL reference clocks for EMIF IP.
OCT
- For DDR4, you must constrain the RZQ pin to pin index 2 in lane AC2.
- Every EMIF instance requires its own dedicated RZQ pin.
- The sharing of RZQ pins is not permitted.
Address and Command
- For DDR4, you must constrain the ALERT_N pin to the address and command lanes only.
- In three-lane address and command schemes, you can place the ALERT_N pin at pin index 8 in lane AC2 only.
- In four-lane address and command schemes, you can place the ALERT_N pin at pin index 8 in lane AC2 or at pin index 8 in lane AC3. When you generate the IP, the resulting RTL specifies which connection to use.
DQS/DQ/DM
For DDR4 x8 DQS grouping, the following rules apply:
- You may use pin indices 0, 1, 2, 3, 8, 9, 10, and 11 within a lane for DQ mode pins only.
- You must use pin index 4 for the DQS_T pin only.
- You must use pin index 5 for the DQS_C pin only.
- You must ensure that pin index 7 remains unused. Pin index 7 is not available for use as a general purpose I/O.
- You must use pin index 6 for the DM/DBI_N pin only.
For DDR4 x4 DQS grouping, the following rules apply:
- You may use pin indices 0, 1, 2, and 3 within a lane for DQ mode pins for the lower nibble only. Pin rotation within this group is permitted.
- You must use pin index 4 for the DQS_T pin only of the lower nibble.
- You must use pin index 5 for the DQS_C pin only of the lower nibble.
- You may use pin indices 8, 9, 10, and 11 within a lane for the DQ mode pins only for the upper nibble.
- Pin rotation within this group is permitted.
- You must use pin index 6 for the DQS_T pin only of the upper nibble.
- You must use pin index 7 for the DQS_C pin only of the upper nibble.