External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 11/18/2024
Public

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Ixiasoft

Document Table of Contents

2.1. Agilex™ 5 EMIF IP Protocol and Feature Support

  • The Agilex™ 5 FPGA EMIF IP supports DDR4 with hard memory controller and hard PHY.
  • The Agilex™ 5 FPGA EMIF IP supports LPDDR4 with hard memory controller and hard PHY.
  • The Agilex™ 5 FPGA EMIF IP supports LPDDR5 with hard memory controller and hard PHY.
  • The Agilex™ 5 FPGA EMIF IP supports DDR5 with hard memory controller and hard PHY (for D-Series and E-Series Device Group A).