External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 11/18/2024
Public
Document Table of Contents

7.5.1.2. DIMM Options

DDR5 unbuffered DIMMs (UDIMMs) and small outline DIMMs (SODIMMs) command and address pins are clocked at single data rate (SDR). DDR5 registered DIMMs (RDIMMs) command and address pins are clocked at double data rate (DDR).

The table below shows a pin comparison of UDIMM, SODIMM, and RDIMM modules up to dual rank. You should always check your memory vendor’s data sheet to be sure.

Table 172.  UDIMM, SODIMM, and RDIMM Pin Options for DDR5
Pins UDIMM Pins SODIMM Pins RDIMM Pins
Data

72 bit

DQ[31:0]_A

DQ[31:0]_B

CB[3:0]_A

CB[3:0]_B

72 bit

DQ[31:0]_A

DQ[31:0]_B

CB[3:0]_A

CB[3:0]_B

80 bit

DQ[31:0]_A

DQ[31:0]_B

CB[7:0]_A

CB[7:0]_B

Data Mask

DM[3:0]_A_n(1)

DM[3:0]_B_n(1)

DM[3:0]_A_n(1)

DM[3:0]_B_n(1)

DM[4:0]_A_n(1)

DM[4:0]_B_n(1)

Data Strobe

x8:

DQS[4:0]_A_t

DQS[4:0]_A_c

DQS[4:0]_B_t

DQS[4:0]_B_c

x8:

DQS[4:0]_A_t

DQS[4:0]_A_c

DQS[4:0]_B_t

DQS[4:0]_B_c

x8:

DQS[4:0]_A_t

DQS[4:0]_A_c

DQS[4:0]_B_t

DQS[4:0]_B_c

x4:

DQS[9:0]_A_t

DQS[9:0]_A_c

DQS[9:0]_B_t

DQS[9:0]_B_c

Command / Address

CA[12:0}_A

CA[12:0}_B

CA[1:0}_A_n

CA[1:0}_B_n

CA[12:0}_A

CA[12:0}_B

CA[1:0}_A_n

CA[1:0}_B_n

CA[6:0]_A

CA[6:0]_B

CS[1:0]_A_n

CS[1:0]_B_n

Clock

CK[1:0]_A_t

CK[1:0]_A_c

CK[1:0]_B_t

CK[1:0]_B_c

CK[1:0]_A_t

CK[1:0]_A_c

CK[1:0]_B_t

CK[1:0]_B_c

CK_t

CK_c

Parity

ALERT_n

ALERT_n

ALERT_n

PAR_A

PAR_B

Other Pins

RESET_n

HSDA, HSCL, HSA

RESET_n

HSDA, HSCL, HSA

RESET_n

HSDA, HSCLL, HSA

LBD/RSP_A_n

LBS/RSP_B_n

Notes to Table:

  1. DM pins are available only for DIMMs constructed using x8 or greater components.
  2. The Agilex™ 5 memory controller supports up to 2 ranks per channel. Agilex™ 5 devices support only 1 DIMM per channel (1DPC).