External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 11/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Agilex™ 5 FPGA EMIF IP - Mailbox Support 14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR4 4.6. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_reset_n_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. s1_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s1_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s1_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. mem_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_ck_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_i3c for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. oct_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR4 x
4.5.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR4 4.5.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR4
4.6. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5 x
4.6.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.6.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.4. Agilex™ 5 EMIF Pin Swapping Guidelines
6.3. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 5 FPGA EMIF IP Resources 6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.3.1. Agilex™ 5 FPGA EMIF IP Resources x
6.3.1.1. OCT 6.3.1.2. PLL
6.3.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.3.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.3.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.3.2.1.2. Estimating Pin Requirements 6.3.2.1.3. Maximum Number of Interfaces
6.3.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.3.3.1. Address and Command Pin Placement for DDR4 6.3.3.2. DDR4 Data Width Mapping 6.3.3.3. General Guidelines 6.3.3.4. x4 DIMM Implementation 6.3.3.5. Specific Pin Connection Requirements 6.3.3.6. Command and Address Signals 6.3.3.7. Clock Signals 6.3.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.4.1. DDR4 Byte Lane Swapping 6.4.2. DDR4 Address and Command and CLK Lane 6.4.3. DDR4 Interface x8 Data Lane 6.4.4. DDR4 Interface x4 Data Lane
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. PHY DFE Tap Bias Values for DDR5 7.4. MEM DFE Tap Bias Values for DDR5 7.5. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.5. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.5.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.5.2. Agilex™ 5 FPGA EMIF IP Resources 7.5.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.5.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.5.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.5.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.5.1.1. Estimating Pin Requirements 7.5.1.2. DIMM Options 7.5.1.3. Maximum Number of Interfaces
7.5.2. Agilex™ 5 FPGA EMIF IP Resources x
7.5.2.1. OCT 7.5.2.2. PLL
7.5.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.5.3.1. General Guidelines - DDR5 7.5.3.2. x4 DIMM Implementation 7.5.3.3. Specific Pin Connection Requirements 7.5.3.4. Command and Address Signals 7.5.3.5. Clock Signals 7.5.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.5.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.5.4.1. Address and Command Pin Placement for DDR5 7.5.4.2. DDR5 Data Width Mapping
7.5.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.5.5.1. DDR5 Byte Lane Swapping 7.5.5.2. DDR5 Address and Command and CLK Lane 7.5.5.3. DDR5 Interface x8 Data Lane 7.5.5.4. DDR5 Interface x4 Data Lane 7.5.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR4 Parameter Descriptions 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 9.2. PHY DFE Tap Bias Values for LPDDR5 9.3. MEM DFE Tap Bias Values for LPDDR5 9.4. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
9.4. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.4.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.4.2. Agilex™ 5 FPGA EMIF IP Resources 9.4.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.4.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.4.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.4.1.1. Estimating Pin Requirements 9.4.1.2. LPDDR5 Component Options 9.4.1.3. Maximum Number of Interfaces
9.4.2. Agilex™ 5 FPGA EMIF IP Resources x
9.4.2.1. OCT 9.4.2.2. PLL
9.4.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.4.3.1. General Guidelines - LPDDR5 9.4.3.2. Specific Pin Connection Requirements 9.4.3.3. Command and Address Signals 9.4.3.4. Clock Signals
9.4.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.4.4.1. Address and Command Pin Placement for LPDDR5 9.4.4.2. LPDDR5 Data Width Mapping 9.4.4.3. LPDDR5 Byte Lane Swapping
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Interface Standard 11.2. Bank Management Efficiency 11.3. Data Transfer 11.4. Improving Controller Efficiency
11.4. Improving Controller Efficiency x
11.4.1. Frequency of Operation 11.4.2. Series of Reads or Writes
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Create a Simplified Design that Demonstrates the Same Issue 12.11. Measure Power Distribution Network 12.12. Measure Signal Integrity and Setup and Hold Margin 12.13. Vary Voltage 12.14. Operate at a Lower Speed 12.15. Determine Whether the Issue Exists in Previous Versions of Software 12.16. Determine Whether the Issue Exists in the Current Version of Software 12.17. Try A Different PCB 12.18. Try Other Configurations 12.19. Debugging Checklist 12.20. Categorizing Hardware Issues 12.21. Signal Integrity Issues 12.22. Characteristics of Signal Integrity Issues 12.23. Evaluating Signal Integrity Issues 12.24. Skew 12.25. Crosstalk 12.26. Power System 12.27. Clock Signals 12.28. Address and Command Signals 12.29. Read Data Valid Window and Eye Diagram 12.30. Write Data Valid Window and Eye Diagram 12.31. Hardware and Calibration Issues 12.32. Memory Timing Parameter Evaluation 12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support x
13.1. Agilex™ 5 Mailbox Structure and Register Definitions 13.2. Sending a Mailbox Command
13.1. Agilex™ 5 Mailbox Structure and Register Definitions x
13.1.1. Mailbox Supported Commands 13.1.2. Mailbox Command Definitions 13.1.3. ECC Syndrome Codes
13.2. Sending a Mailbox Command x
13.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Using Mailbox 13.2.2. Example 2: Reading the Memory Clock Frequency for an Interface 13.2.3. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support
14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

6.3.3.2. DDR4 Data Width Mapping

Agilex™ 5 devices do not support flexible data lanes placement. Only fixed byte lanes within the HSIO bank can be used as data lanes. The following table lists the supported address and command and data lane placements in an HSIO bank.
Table 140.  DDR4 Data Width Mapping
Controller Address/Command Scheme Data Width Usage BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Primary Scheme 2 DDR4 x16 GPIO 2 GPIO 2 GPIO 2 DQ[1] AC2 AC1 AC0 DQ[0]
Scheme 1 GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 1a GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3 GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3a GPIO 2 GPIO 2 DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 2 DDR4 x16 + ECC GPIO 2 GPIO 2 DQ[ECC] DQ[1] AC2 AC1 AC0 DQ[0]
Scheme 1 GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 1a GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3 GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 3a GPIO 2 DQ[ECC] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 2 DDR4 x32 GPIO 2 DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
Scheme 1 DQ[3] DQ[2] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 1a DQ[3] DQ[2] DQ[1] DQ[0] AC2 AC1 AC0 AC3
Scheme 2 DDR4 x32 + ECC DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
Primary + Secondary Scheme 2 DDR4 x40 1 sDQ[0] wDQ[3] wDQ[2] wDQ[1] AC2 AC1 AC0 wDQ[0]
Note:
  1. This configuration is not supported on E-Series devices. DDR4 x40 requires both controllers within an I/O bank in a lockstep configuration, and AXI user data.
  2. GPIO – available for GPIO/PHYLite.
  3. DQ[ECC] – DQ/DQS group used as ECC.
  4. ES0 silicon supports address/command pin placement for DDR4 on the bottom sub-bank (BL0-BL3) only.
Table 141.  D-Series Supported DDR4 Mapping for Lockstep Configuration for x64
A/C A/C Placement Option BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
  Primary Secondary
3 AC Pri Top Sub-Bank / Sec DQ Bot DQ[0] DQ[3] DQ[2] DQ[1] AC1 AC2 AC0 GPIO DQ[7] DQ[6] DQ[5] DQ[4] GPIO GPIO GPIO GPIO
AC Pri Bot Sub-Bank / Sec DQ Bot DQ[0] AC0 AC1 AC2 DQ[1] DQ[2] DQ[3] GPIO DQ[7] DQ[6] DQ[5] DQ[4] GPIO GPIO GPIO GPIO
AC Pri Top Sub-Bank / Sec DQ Top(m) DQ[0] DQ[3] DQ[2] DQ[1] AC1 AC2 AC0 GPIO GPIO X X X DQ[4] DQ[5] DQ[6] DQ[7]
4 AC Pri Top Sub-Bank / Sec DQ Bot(m) DQ[3] DQ[2] DQ[1] DQ[0] AC1 AC2 AC0 AC3 DQ[7] DQ[6] DQ[5] DQ[4] GPIO GPIO GPIO GPIO
AC Pri Top Sub-Bank / Sec DQ Top(m) DQ[3] DQ[2] DQ[1] DQ[0] AC1 AC2 AC0 AC3 GPIO X X X DQ[4] DQ[5] DQ[6] DQ[7]
AC Pri Bot Sub-Bank / Sec DQ Top(m) AC3 AC0 AC1 AC2 DQ[0] DQ[1] DQ[2] DQ[3] GPIO X X X DQ[4] DQ[5] DQ[6] DQ[7]
Note:
  • GPIO = available for GPIO/PHYLite.
  • X = not available for GPIO/PHYLite.
Table 142.  D-Series Supported Lockstep configuration for DDR4 x72 or x64 (with ECC)
A/C A/C Placement Option BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
  Primary Secondary
3 AC Pri Top Sub-Bank / Sec DQ Bot DQ[4] DQ[3] DQ{2] DQ[1] AC1 AC2 AC0 sDQ[0] DQ[8] DQ[7] DQ[6] DQ[5] GPIO GPIO GPIO GPIO
AC Pri Bot Sub-Bank / Sec DQ Bot DQ[0] AC0 AC1 AC2 DQ[1] DQ[2] DQ[3] sDQ[4] DQ[8] DQ[7] DQ[6] DQ[5] GPIO GPIO GPIO GPIO
AC Pri Top Sub-Bank / Sec DQ Top(m) DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC0 sDQ[0] GPIO X X X DQ[5] DQ[6] DQ[7] DQ[8]
4 AC Pri Top Sub-Bank / Sec DQ Bot(m) DQ[3] DQ[2] DQ[1] DQ[0] AC1 AC2 AC0 AC3 DQ[8] DQ[7] DQ[6] DQ[5] X X GPIO sDQ[4]
AC Pri Top Sub-Bank / Sec DQ Top(m) DQ[3] DQ[2] DQ[1] DQ[0] AC1 AC2 AC0 AC3 DQ[4] X X X DQ[5] DQ[6] DQ[7] sDQ[8]
AC Pri Top Sub-Bank / Sec DQ Top(m) AC3 AC0 AC1 AC2 DQ[0] DQ[1] DQ[2] DQ[3] DQ[4] X X X DQ[5] DQ[6] DQ[7] sDQ[8]
  • GPIO = available for GPIO/PHYLite.
  • X = not available for GPIO/PHYLite.
  • DQ lane with an s prefix is the lane used for the following:
    • WUSER/RUSER in x72 configuration or
    • ECC Lane for x64 + ECC configuration

Level Two Title