External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

6.2.1.1. OCT

You require an OCT calibration block if you are using an Agilex™ 5 FPGA OCT calibrated series, parallel, or dynamic termination for any I/O in your design. There are two OCT blocks in an HSIO bank, one for each sub-bank.

You must observe the following requirements when using OCT blocks:

  • The I/O bank where you place the OCT calibration block must use the same VCCIO_PIO voltage as the memory interface.
  • The OCT calibration block uses a single fixed RZQ. You must ensure that an external termination resistor is connected to the correct pin for a given OCT block.