External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 11/18/2024
Public
Document Table of Contents

4.4.15. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM

Reset pin to the memory. Must always be placed along with channel 0, but shared for entire interface (all channels within one EMIF).

Table 76.  Interface: mem_reset_nInterface type: conduit
Port Name Direction Description
mem_0_reset_n Output Asynchronous Reset channel 0.