Visible to Intel only — GUID: qsx1683566196545
Ixiasoft
Visible to Intel only — GUID: qsx1683566196545
Ixiasoft
3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
To enable connectivity between the HPS and the Agilex™ 5 EMIF IP, you must create and configure an instance of the EMIF for HPS IP, and connect it to the Agilex™ 5 FPGA hard processor subsystem instance in your system.
Restrictions on I/O Bank Usage for Agilex™ 5 EMIF IP with HPS
The following restrictions apply to the I/O bank usage:
- Only the two IO96 banks adjacent to the HPS MPFE can be used for HPS-EMIF. (Banks 3A and 3B.)
- If only one IO96 bank is to be used by HPS-EMIF, it must be the one adjacent to the HPS MPFE. (Bank 3A.)
-
No protocol's data width usage may span multiple IO96 banks. For example, a single DDR4 x64, which requires 8 byte lanes for data and 3 byte lanes for address and control, may not span two IO96 banks. However, a single DDR4 x32, which requires 4 byte lanes of data and 3 byte lanes of address and control, may be placed in one IO96 bank and another single DDR4 x32 may be placed in another IO96 bank.
- Unused pins in an HPS-EMIF occupied IO96 bank must be left unused; you cannot use them as general-purpose I/O pins.
- Unused lanes in an HPS-EMIF occupied IO96 bank must be left unconnected; you cannot use them as general-purpose I/O pins.
- HPS-EMIF and AVSTx16 configuration mode cannot be used simultaneously, because both use bank 3A.
- Reference clock sharing is not allowed between HPS-EMIF IP and other IPs.
- For multi-channel EMIFs or when multiple EMIFs are used inside HPS-EMIF IP, they must have identical IP parameters.
Protocol | Channel | Data Width | BL7 | BL6 | BL5 | BL4 | BL3 | BL2 | BL1 | BL0 |
---|---|---|---|---|---|---|---|---|---|---|
DDR4 | Single | x16 | – | – | – | DQ[1] | AC2 | AC1 | AC0 | DQ[0] |
Single | x16+ECC | – | – | DQ[ECC] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Single | x32 | – | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Single | x32+ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Dual 1 | x32 | – | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Dual 1 | x32+ECC | DQ[ECC] | DQ[3] | DQ[2] | DQ[1] | AC2 | AC1 | AC0 | DQ[0] | |
Single | x64 | Not supported | ||||||||
Single | x64+ECC | Not supported | ||||||||
1 Uses two IO96 banks adjacent to the HPS MPFE. | ||||||||||
DDR5 | Single | x16 | – | – | – | – | AC1 | AC0 | DQ[0] | DQ[1] |
Single | x16 | DQ[1] | DQ[0] | AC1 | AC0 | – | – | – | – | |
Dual | x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[0] | DQ[1] | |
Single | x16+ECC | – | – | – | DQ[ECC] | AC1 | AC0 | DQ[0] | DQ[1] | |
Single | x32 | – | – | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
Single | x32+ECC | – | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
Dual 1 | x32 | – | – | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
Dual 1 | x32+ECC | – | DQ[ECC] | DQ[3] | DQ[2] | AC1 | AC0 | DQ[0] | DQ[1] | |
1 Uses two IO96 banks adjacent to the HPS MPFE. | ||||||||||
LPDDR4 | Single | x16 | – | – | – | – | AC1 | AC0 | DQ[1] | DQ[0] |
Dual | x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
Quad 1 | x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
Single | x32 | DQ[3] | DQ[2] | – | – | AC1 | AC0 | DQ[1] | DQ[0] | |
Dual 1 | x32 | DQ[3] | DQ[2] | – | – | AC1 | AC0 | DQ[1] | DQ[0] | |
1 Uses two IO96 banks adjacent to the HPS MPFE. | ||||||||||
LPDDR5 | Single | x16 | – | – | – | – | AC1 | AC0 | DQ[1] | DQ[0] |
Dual | x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
Quad 1 | x16 | DQ[1] | DQ[0] | AC1 | AC0 | AC1 | AC0 | DQ[1] | DQ[0] | |
Single | x32 | DQ[3] | DQ[2] | – | – | AC1 | AC0 | DQ[1] | DQ[0] | |
Dual 1 | x32 | DQ[3] | DQ[2] | – | – | AC1 | AC0 | DQ[1] | DQ[0] | |
1 Uses two IO96 banks adjacent to the HPS MPFE. |