External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support

The Agilex™ 5 FPGA family consists of 2 series: E-Series and D-Series. The following table summarizes the protocol and maximum data width support for E-Series and D-series devices.
Table 3.  Protocol and Data Width Support for Fabric EMIF
Protocol Maximum Data Width
E-Series Device Group A E-Series Device Group B D-Series
DDR4 x32 + ECC x32 + ECC

x72 (DIMM)

x32 + ECC (Component)

x40 (Component)

LPDDR4

4ch x16

2ch x16

1ch x32

4ch x16

2ch x16

1ch x32

4ch x16

2ch x16

1ch x32

DDR5 x32 + ECC

2 x36 (UDIMM/SODIMM)

2 x40 (RDIMM)

x32 + ECC (Component)

LPDDR5

4ch x16

2ch x16

1ch x32

4ch x16

2ch x16

1ch x32

4ch x16

2ch x16

1ch x32

DIMM Support No No Yes
Table 4.  Protocol and Data Width Support for HPS EMIF
Protocol Maximum Data Width
E-Series Device Group A E-Series Device Group B D-Series
DDR4 x32 + ECC x32 + ECC x32 + ECC
DDR5 x32 + ECC x32 + ECC
LPDDR4 4ch x 16, 2ch x 16, 1ch x 32 4ch x 16, 2ch x 16, 1ch x 32 4ch x 16, 2ch x16, 1ch x 32
LPDDR5 4ch x 16, 2ch x 16, 1ch x 32 4ch x 16, 2ch x 16, 1ch x 32 4ch x 16, 2ch x 16, 1ch x 32
DIMM Support No No Yes
Note:
  • E-Series devices support only component interfaces; they do not support DIMMs. For E-Series, DDR5 is supported on Device Group A only.
  • Agilex™ 5 FPGAs do not support DDR4 and DDR5 interface widths of 8.
  • The current version of the Agilex™ 5 External Memory Interface IP supports DDR4, LPDDR4, DDR5, and LPDDR5 memory protocols.
  • LPDDR5 on Agilex 5 E-Series Device Group B can support only one frequency set point (FSP0).
  • You can only use asynchronous fabric clocking mode with the DDR5 protocol on -3 speed bin for E-Series Device Group A and D-Series devices.