External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

6.3.1. DDR4 Byte Lane Swapping

The data lane can be swapped when the byte-lanes are utilized as DQ/DQS pins. Byte lane swapping on utilized lanes is allowed when you swap all the DQ/DQS/DM/DBI pins in the same byte lane with the other utilized byte lane.

The rules for swapping DQ byte lane are as follows:

  • You can only swap between utilized DQ lanes.
  • You cannot swap a DQ lane with an AC lane.
  • You cannot swap a DQ lane with an ECC lane when out-of-band ECC is enabled. For x40 interfaces, the highest-indexed DQ byte lane cannot be swapped.
  • Additional restrictions apply when you use a x16 memory component:
    • You must place DQ group 0 and DQ group 1 on adjacent byte lanes, unless they are separated by AC Lanes. These 2 groups must be connected to the same x16 memory component.
    • You must place DQ group 2 and DQ group 3 on adjacent byte lanes, unless they are separated by AC Lanes. These 2 groups must be connected to the same x16 memory component.
    • If you use only one byte of the x16 memory component, you must use only the lower byte of the memory component.
  • Additional restrictions apply in lockstep configuration implemented with 2 adjacent IO96 banks:
    • Any DQ lane with a letter s prefix must remain in its designated byte lane. You cannot swap an sprefixed DQ lane with any other byte-lane.
    • DQ lane swapping between IO96 banks is not allowed. You can only swap between utilized DQ lanes within the same IO96 bank.
Table 102.  Byte Lane Swapping
Address/Command Scheme Data Width usage BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Scheme 2 DDR4 x32 + ECC DQ[ECC] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]
Scheme 2 DDR4 x40 DQ[4] DQ[3] DQ[2] DQ[1] AC2 AC1 AC0 DQ[0]

Example: DDR4 x 32 +ECC implemented with AC Scheme 2

BL7 is used as ECC DQ lane, while Lane 0, 4, 5 and 6 are used DQ lanes. Byte lane swapping between BL0,4,5,6 is allowed.

Example: DDR4 x 40 implemented with AC Scheme 2

BL0,4,5,6,7 are used as DQ lanes. Byte lane swapping between BL0,4,5,6 is allowed. The highest-index DQ byte lane (that is, DQ[4]), cannot be swapped and must be placed at BL7.

Table 103.  Byte Lane Swapping for Lockstep Configuration
A/C Placement Option BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7 BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
Primary Secondary
AC Pri Top Sub-Bank / Sec DQ Bot DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC0 sDQ[0] DQ[8] DQ[7] DQ[6] DQ[5] GPIO GPIO GPIO GPIO
AC Pri Bot Sub-Bank / Sec DQ Bot DQ[0] AC0 AC1 AC2 DQ[1] DQ[2] DQ[3] sDQ[4] DQ[8] DQ[7] DQ[6] DQ[5] GPIO GPIO GPIO GPIO
AC Pri Top Sub-Bank / Sec DQ Top(m) DQ[4] DQ[3] DQ[2] DQ[1] AC1 AC2 AC0 sDQ[0] GPIO X X X DQ[5] DQ[6] DQ[7] DQ[8]

Example: x72 or x64+ECC Configuration with AC Pri Top Sub-Bank/Sec DQ Bot Placement

In Primary IO96 Bank: sDQ[0] is used for ECC or RUSER/WUSER. It cannot be swapped to other byte lanes.

Byte lane swapping between BL0, 1,2 and 3 is allowed.

In Secondary IO96 Bank: BL0,1,2,3 are used as DQ lanes. Byte lane swapping between BL0,1,2,3 is allowed.

Example: x72 or x64+ECC Configuration with AC Pri Bot Sub-Bank/Sec DQ Bot Placement

In Primary IO96 Bank: sDQ[4] is used for ECC or RUSER/WUSER. It cannot be swapped to other byte lanes.

Byte lane swapping between BL0, 4,5 and 6 is allowed.

In Secondary IO96 Bank: BL0,1,2,3 are used as DQ lanes. Byte lane swapping between BL0,1,2,3 is allowed.

Example: x72 or x64+ECC Configuration with AC Pri Top Sub-Bank / Sec DQ Top(m)

In Primary IO96 Bank: sDQ[0] is used for ECC or RUSER/WUSER. It cannot be swapped to other byte lanes.

Byte lane swapping between BL0, 1,2 and 3 is allowed.

In Secondary IO96 Bank: BL4,5,6,7 are used as DQ lanes. Byte lane swapping between BL4,5,6,7 is allowed.