External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

12.28. Address and Command Signals

Confirm that address and command signals are reaching the memory devices correctly.

For example, if you are targeting DDR4, you can probe the ALERT_N pin after the memory interface has been successfully calibrated, to determine if any memory component has encountered an address and command parity error.