MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 4/26/2024
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Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

1.1. Generating the Design

Use the MIPI CSI-2 Intel® FPGA IP parameter editor in the Quartus® Prime software to generate the design example.
Figure 2. Procedure
Figure 3. Design Example Tab
  1. Select Tools > IP Catalog and select Agilex™ 5 as the target device family.
    Note: The design example only supports Agilex™ 5 devices.
    The IP parameter editor appears.
  2. In the IP Catalog, locate and double-click MIPI CSI-2 Intel FPGA IP.
    The New IP Variant or New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip/<your_ip>.qsys.. Click OK.
    The IP parameter editor appears.
  4. In the Design Example tab, select Synthesis and/or Simulation to generate the design example.
    Note: For this release, only the Synthesis option is available to generate MIPI CSI-2 RX-only Design Example files for Quartus® Prime compilation. Simulation is not yet supported for MIPI CSI-2 RX-only Design Example.
  5. Under Generate File Format, select Verilog or VHDL.
  6. Under Target Development Kit, No development kit is set by default and the Target Device is set to Agilex™ 5 devices. The default device OPN is automatically selected based on the target device of the project to match the device on this development kit.
  7. Click the Generate Example Design button to generate the project files.

Section Content
Design Example Parameters

Level Two Title