MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.5. Simulation

The example design simulation demonstrates the correct way to drive data onto the AXI-Stream bus of the CSI-2 TX and to demonstrate correct data reception of the AXI-Stream bus of the CSI-2 RX.

The simulation is designed to run either in video mode which has the AXI-Stream bus complying with the Intel Video Streaming Protocol, or in passthrough mode which uses the MIPI CSI-2 protocol to define how the data is presented on the AXI-Stream Bus.

The simulation generates the correct signals and Data on the AXI-Stream Bus input of the CSI-2 TX core. This then passes through the CSI-2 TX and out of the PPI interface of the CSI-2 TX. The PPI interface is then looped back into the PPI interface of the CSI-2 RX core. The data passes through the CSI-2 RX core and then out of the AXI-Stream interface. The signals and Data on the AXI-Stream Bus of the CSI-2 RX core are then checked to make sure they match what is expected.


Section Content
Data Signal Checking
Verification
Display Messages
Waveform Plotting
Structure
Known Limitations

Level Two Title