MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2. MIPI CSI-2 Intel® FPGA IP Design Example

The MIPI CSI-2 Intel® FPGA IP core has two Design Example variants for Agilex™ 5 devices, namely MIPI CSI-2 RX+TX Subsystem and MIPI CSI-2 RX-only.
Features Included in the MIPI CSI-2 Example Design
Feature Support Range
Direction RX, TX
D-PHY Lanes 1, 2, 4, 8
Bits per Lane 16
Pixels in parallel 1, 2, 4
Video Data Format YUV420 8-bit(legacy), YUV420 8-bit, YUV420 10-bit, YUV422 8-bit, YUV422 10-bit, RGB888, RGB666, RGB565, RGB555, RGB444, RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, RAW16, RAW20 & RAW24
Buffer Depth 128, 256, 512, 1024, 2048, 4096, 8192, 16384

Section Content
Agilex 5 MIPI CSI-2 RX+TX Subsystem Design Features
Agilex 5 MIPI CSI-2 RX-only Design Features
Software Requirements
Functional Description
Simulation

Level Two Title