MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.5.5.2. Device Under Test (DUT) Wrapper

The DUT Wrapper contains the devices to be tested as well as some basic interface logic to connect to the test generator in the top level testbench.
Figure 9. Device Under Test (DUT) Wrapper
Level Two Title