MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.4.2. Reset Scheme

Table 7.  MIPI CSI-2 Intel® FPGA IP Reset Scheme
Reset Signal Associated Clock Domain Description
rst_controller_reset_out_reset axi_clock_bridge_in_clk_clk This is MIPI CSI-2 AXI4-Streaming video input reset signal. Asserting this reset will trigger a reset to all the blocks running at axi4s_clk clock domain.
mipi_dphy_arst_reset_n mipi_dphy_ref_clk_0_clk This is MIPI D-PHY system input reset signal which is exported from MIPI D-PHY IP. For more information, refer to the MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs.
mipi_dphy_reg_srst_reset_n dphy_clock_bridge_in_clk_clk This is MIPI D-PHY AXI-Lite synchronous input reset signal which is exported from MIPI D-PHY IP. For more information, refer to the MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs.
mipi_dphy_LINK0_link_core_srst_reset_n mipi_dphy_LINK0_link_core_clk_clk This is MIPI D-PHY synchronous / asynchronous output reset signal for Link n which are exported from MIPI D-PHY IP. For more information, refer to the MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs.
mipi_dphy_LINK0_link_core_arst_reset_n mipi_dphy_LINK0_link_core_clk_clk
mipi_dphy_LINK1_link_core_srst_reset_n mipi_dphy_LINK1_link_core_clk_clk
mipi_dphy_LINK1_link_core_arst_reset_n mipi_dphy_LINK1_link_core_clk_clk
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