MIPI CSI-2 Intel® FPGA IP Design Example User Guide

Download PDF
ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.4.1. Design Components

Table 6.  MIPI CSI-2 Intel® FPGA IP Design Components
Component Description
MIPI CSI-2 RX Sub-system

The CSI-2 RX sub-system consists of:

  • MIPI RX Protocol – The MIPI RX Protocol consists of multiple layers such as the lane management layer, low level protocol and byte to pixel conversion. The MIPI RX Protocol receives standard PHY-Protocol Interface (PPI) data signals which are processed by the low-level protocol module to extract the real video information. This module interconnects between D-PHY RX PPI interfaces to the CSI-2 RX core.
  • Clocked Video to AXI convertor (CV2AXI) – This module converts clocked video data to AXI4-Streaming video data and interfaces with the CSI-2 RX sub-system.
  • Control and Status Register (CSR Control MUX) – This module resides at the higher layer to multiplex the control operation between both MIPI RX protocol and CV2AXI CSR submodules.

The interfaces of CSI-2 RX sub-system:

  • PPI – This PPI data signals interconnects between D-PHY RX and CSI2-RX core.
  • Clock Source – The clock source to CSI-2 RX: axi4s_clk.
  • Avalon® memory-mapped interface Pipeline Bridge – This Avalon® memory-mapped interface bridge interface is exported from CSI-2 RX sub-system.
  • AXI4 Video Streaming – This interface from CV2AXI submodule is exported out from CSI-2 RX sub-system.
  • PPI RX Error – This interface is output signals from D-PHY RX to CSI-2 RX core. These signals are not utilized in CSI-2 RX core, thus these are exported from CSI-2 RX sub-system.
MIPI CSI-2 TX Sub-system

The CSI-2 TX sub-system consist of:

  • MIPI TX Protocol – The MIPI TX Protocol consists of multiple layers such as the lane distribution layer, low level protocol and pixel to byte conversion. The MIPI TX Protocol transmits standard PPI data signals which are processed by the low-level protocol module from the extraction real video information. This module interconnects between DPHY TX PPI interfaces to the CSI-2 TX core.
  • AXI to Clocked Video convertor (AXI2CV) – This module interfaces with the CSI-2 TX sub-system and converts AXI4-Streaming video data to clocked video data.
  • Control & Status Register (CSR Control MUX) – This module resides at the higher layer to multiplex the control operation between both MIPI TX protocol and AXI2CV CSR submodules.

The interfaces of CSI-2 TX sub-system:

  • PHY-Protocol Interface (PPI) – This PPI data signals interconnects between DPHY TX and CSI2-TX core.
  • Clock Source – The clock source to CSI-2 TX: axi4s_clk
  • Avalon memory-mapped Pipeline Bridge – This Avalon memory-mapped bridge interfaces are exported from CSI-2 TX sub-system.
  • AXI4 Video Streaming – This interface to AXI2CV submodule is imported to CSI-2 TX sub-system.
MIPI D-PHY RX Sub-system

The interfaces of D-PHY RX sub-system consist of:

  • PPI – This PPI data signals interconnects between D-PHY RX and CSI2-RX core.
  • Clock Source – The clock source to D-PHY RX: ref_clk_0 and reg_clk.
  • Serial data connect to the LINK D-PHY I/O signals of D-PHY RX.
  • D-PHY AXI Lite Register Bus - This configuration and status registers implemented by the D-PHY PCS layer and exported from D-PHY sub-system.
  • D-PHY Register Bus Output – This output interface is exported from D-PHY sub-system.
MIPI D-PHY TX Sub-system

The interfaces of D-PHY TX sub-system:

  • PHY-Protocol Interface (PPI) – This PPI data signals interconnects between D-PHY TX and CSI2-TX core.
  • Clock Source – The clock source to D-PHY TX: ref_clk_0 and reg_clk.
  • Serial data connect to the LINK DPHY IO signals of D-PHY RX.
  • D-PHY AXI Lite Register Bus - This configuration & status registers implemented by the D-PHY PCS layer and exported from DPHY sub-system.
  • D-PHY Register Bus Output – This output interface is exported from D-PHY sub-system.
Reset Release IP This Reset Release IP is used to manage reset for full FPGA core configurations which connect where the output is connected to Reset Controller and Reset Controller_001. The FPGA asserts the INIT DONE output to signal that the device is fully in user mode.
AXI4S Clock Bridge The Clock Bridge IP is used to export MIPI CSI-2 AXI4-Streaming video clock (axi4s_clk) clock signal out of the system to MIPI CSI-2 RX core and MIPI CSI-2 TX core.
D-PHY Clock Bridge The Clock Bridge IP is used to export MIPI D-PHY AXI-Lite clock (reg_clk) clock signal out of the system to MIPI D-PHY core.
Level Two Title