MIPI CSI-2 Intel® FPGA IP Design Example User Guide

Download PDF
ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

2.5.3. Display Messages

The messages displayed when the simulation is run are designed to give helpful information about what the simulation is doing while it is running. The simulation transfers a large number of bytes using a large number of packets, it is not useful to provide information about all of these. Instead, messages are provided for significant events that represent the test set-up of 10 frames with a resolution of 128x96.

Some of these messages are dependent on whether the simulation is being run in video or passthrough mode.

In video mode, the simulation messages provide information from the Intel Video Streaming Protocol. These include:
  • Sending and receiving of VVP Image Information Packets
  • Receiving of VVP start of a new field of video
  • Sending and receiving of VVP End-of-Field Packets

With the test set up for transmission of 10 frames, we expect to receive 10 VVP Image Information Packets, start of a new field of video and End-of-Field Packets.

In video mode, the first five image frames are consumed by the MIPI CSI-2 RX IP Core. This is done so that the RX IP Core can lock to the video resolution and ensure a stable video stream. The five frames are sent in addition to the 10 in the simulation.

In passthrough mode:
  • Receiving of a MIPI CSI-2 Frame Start (FS) Short Packet
  • Receiving of a MIPI CSI-2 Frame End (FE) Short Packet
Level Two Title