MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Subsystem Design Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

1.1.1. Design Example Parameters

Table 1.  MIPI CSI-2 Intel® FPGA IP Design Example Parameters for Agilex™ 5 Devices
Parameter Value Description
Available Design Example
Select Design
  • MIPI CSI-2 RX-only
  • MIPI CSI-2 RX+TX
 Select the design example to be generated.
  • MIPI CSI-2 RX-only: This design demonstrates the connection between one CSI-2 Rx and a MIPI D-PHY in a Platform Designer subsystem.
  • MIPI CSI-2 RX+TX: This design demonstrates the connection between one CSI-2 RX, one CSI-2 TX, and a MIPI D-PHY in a Platform Designer subsystem.
Design Example Files
Synthesis On, Off Turn on this option to generate the necessary files for Quartus® Prime compilation. For this release, this parameter has to be enabled to generate MIPI CSI-2 RX-only Design Example files for Quartus® Prime compilation, since simulation is not yet supported.
Simulation On, Off Turn on this option to generate the necessary files for the MIPI CSI-2 RX+TX Subsystem simulation testbench. For this release, this parameter is only enabled for generating MIPI CSI-2 RX+TX Subsystem simulation testbench. MIPI CSI-2 RX-only Design Example simulation testbench is not yet supported.
Generated HDL Format
Generated File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files such as example testbenches and top level files for hardware demonstration are in Verilog HDL format.
Target Development Kit
Select Board No Development Kit

Select the board for the targeted design example.

No Development Kit: This option excludes all hardware aspects for the design examples. The IP core sets all pin assignments to virtual pins.

Target Device
Change Target Device Off Turn on this option and select the preferred device variant for the development kit.
Note: This option is only available when a Development Kit option is available in Select Board.
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