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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
The parameter options in the Transmitter Settings tab are available if Number of TX channels in the General Settings tab is not 0.
Parameter | Value | Description |
---|---|---|
Enable tx_outclock port |
|
Turn on to expose the tx_outclock port. Default is On.
Turning on this parameter reduces the maximum number of channels per transmitter interface by one channel. |
Desired tx_outclock phase shift (degrees) |
|
Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock. Default is 0. |
Actual tx_outclock phase shift (degrees) | Depends on the Desired tx_outclock phase shift (degrees) input. Refer to related information. |
Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift. |
Tx_outclock division factor | Depends on the SERDES factor. | Specifies the ratio of the fast clock frequency to the outclock frequency. For example, the maximum number of serial transitions per outclock cycle. |
Related Information