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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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3.2. Serializer
The serializer contains a set of registers that captures the parallel data from the core using the LVDS fast clock. The registers then transfers the data to the serializer block. The MSB of the serializer feeds the LVDS SERDES output buffer. Consequently, higher order bits precede lower order bits in the output bitstream.
Figure 4. LVDS SERDES ×8 Serializer Bit PositionThis figure shows the waveforms specific to the serialization factor of 8. These are functional waveforms and do not convey timing information.
Signal | Description |
---|---|
tx_in[7:0] | Data for serialization (Supported serialization factors: 4 and 85 ) |
fast_clock | Clock for the serializer |
tx_out | LVDS SERDES output data stream |
5 Serialization factor of 8 is available only in Agilex™ 5 FPGAs production devices.