LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 10/07/2024
Public
Document Table of Contents

2.2. SERDES Blocks, Modes, and Clock Domains

Figure 2. SERDES CircuitryThis figure shows a transmitter and receiver block diagram for the SERDES circuitry with the interface signals of the transmitter and receiver data paths. The figure shows a transmitter and a receiver sharing an I/O PLL as they are in the same sub-bank and using the same I/O PLL resource. In single data rate (SDR) and double data rate (DDR) modes, the data widths are 1 and 2 bits, respectively.


Table 3.  Supported Modes, Blocks, and Clocks for the Data Paths
Data Path Mode Block Clock Domain
Transmitter TX Serializer SERDES clock domain
Receiver DPA-FIFO DPA DPA clock domain
Synchronizer DPA-SERDES clock domain crossing
Bit Slip SERDES clock domain
Deserializer SERDES clock domain
Non-DPA DPA Not used
Synchronizer Not used
Bit Slip SERDES clock domain
Deserializer SERDES clock domain
Soft-CDR DPA DPA clock domain
Bit Slip DPA clock domain
Deserializer DPA clock domain