Visible to Intel only — GUID: sam1412833580887
Ixiasoft
Visible to Intel only — GUID: sam1412833580887
Ixiasoft
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
Parameter | Value | Description |
---|---|---|
Use external PLL |
|
Turn on to use an external PLL:
Default is Off. This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration. |
Desired inclock frequency | — | Specifies the inclock frequency in MHz. Default is 100.0. |
Actual inclock frequency | — | Displays the closest inclock frequency to the desired frequency that can source the interface. The displayed value changes according to the Desired inclock frequency parameter value. |
FPGA/PLL speed grade | — | Displays the FPGA/PLL speed grade, which determines the operation range of the PLL. The displayed value is based on the device selected in your project. |