LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 10/07/2024
Public
Document Table of Contents

3.3.1.1. Edge-Aligned tx_outclock to tx_out

For rising tx_outclock edge-aligned to the MSB of the serial data on tx_out, specify a 0° phase shift.
Figure 7.  0° Edge Aligned tx_outclock ×8 Serializer Waveform with a Division Factor of 8