LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 10/07/2024
Public
Document Table of Contents

5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode

Figure 29. Non-DPA or DPA LVDS SERDES Receiver Interface with the IOPLL IP without LVDS SERDES Transmitter in the Same Sub-Bank


Figure 30. Non-DPA or DPA LVDS SERDES Receiver Interface with the IOPLL IP with LVDS SERDES Transmitter in the Same Sub-Bank


Figure 31. Soft-CDR LVDS SERDES Receiver Interface with the IOPLL IP without LVDS SERDES Transmitter in the Same Sub-Bank


Figure 32. Soft-CDR LVDS SERDES Receiver Interface with the IOPLL IP with LVDS SERDES Transmitter in the Same Sub-Bank


Figure 33. LVDS SERDES Transmitter Interface with the IOPLL IP


In the external PLL mode, the LVDS SERDES IP automatically turns on the ext_pll_1_outclock2 port. If you do not connect the ext_pll_1_outclock2 port as shown in the preceding figures, the Quartus® Prime compiler outputs error messages.