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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings
5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings
5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings
5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings
5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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3.3.1.2. Center-Aligned tx_outclock to tx_out
To specify a center-aligned relationship between tx_outclock and the MSB of the serial data on tx_out, specify a 180° phase shift.
Figure 8. 180° Center Aligned tx_outclock ×8 Serializer Waveform with a Division Factor of 8
- Phase shift values from 0° to 315° position the rising edge of tx_outclock within the MSB of the tx_out data.
- Phase shift values starting from 360° position the rising edge of tx_outclock in serial bits after the MSB. For example, a 540° phase shift positions the rising edge in the center of the bit after the MSB.
Figure 9. 180° Center Aligned tx_outclock ×8 Serializer Waveform with Division Factor of 2This figure shows a ×8 serialization factor using a 180° phase shift with a tx_outclock division factor of 2 (DDR clock and data relationship).