MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

6.2. CSI-2 Transmitter Register Map

Base address (control_address[9:8]) 0x0 accesses the MIPI CSI-2 transmitter control and status registers. ) Base 0x1 accesses the AXI2CV registers.
Table 28.  CSI-2 Transmitter IP Registers
Address [9:0] Register RW Default Bit Bit Name Description
0x000 CORE_STATUS RO 0x0 31:3 RESERVED Reserved.
LANE‑1 2:0 MAXIMUM_LANES Number of D-PHY lanes configured during IP generation minus 1, e.g. 4 lanes = 3.

0x001 –

0x03

 RESERVED N/A N/A 31:0 RESERVED Reserved.
0x004 GENERIC_SHORT_PACKET_STATUS RO 0x0 31:5 RESERVED Reserved.
4:0 GSP_FIFO_USED Generic short packet FIFO fill level.

0x005 –

0x00F

 RESERVED N/A N/A 31:0 RESERVED Reserved.
0x010 IRQ_STATUS RW1C 0x0 31:3 RESERVED Reserved.
2 GSP_UNSUPPORTED_DT Unsupported CSI-2 Data Type written to generic short packet FIFO.
1 GSP_FIFO_FULL Generic short packet FIFO is full and cannot accept more data.
0 LINE_BUFFER_OVERFLOW TX line buffer has overflowed, with data lost.

0x011 –

0x01F

 RESERVED N/A N/A 31:0 RESERVED Reserved.
0x020 IRQ_ENABLE RW 0x0 31:3 RESERVED Reserved.
2 GSP_UNSUPPORTED_DT_ENA Enable IRQ: Unsupported CSI-2 Data Type written to generic short packet FIFO.
1 GSP_FIFO_FULL_ENA Enable IRQ: Generic short packet FIFO is full and cannot accept more data.
0 RESERVED Reserved.

0x021 –

0x033

 RESERVED N/A N/A 31:0 RESERVED Reserved.
0x034 GENERIC_SHORT_PACKET_WRITE RW 0x0 31:26 RESERVED Reserved.
25:0 GSP_DATA Write a generic short packet to the transmit FIFO. Data should contain the 32-bit packet and a write to this register adds it to the FIFO for insertion.

0x035 –

0x0FF

 RESERVED N/A N/A 31:0 RESERVED Reserved.

0x100 –

0x14F

 RESERVED N/A N/A 31:0 RESERVED Reserved.
0x150 VIDEO_INTF0_STATUS RO 0x0 31:1 RESERVED Reserved.
0 VC0_MODE_MATCH Asserted when the input data resolution is matching with the WIDTH and HEIGHT_F0/HEIGHT_F1 registers for video streaming interface 0.
0x151 VIDEO_INTF1_STATUS RO 0x0 31:1 RESERVED Reserved.
0 VC1_MODE_MATCH Asserted when the input data resolution is matching with the WIDTH and HEIGHT_F0/HEIGHT_F1 registers for video streaming interface 1.
0x152 VIDEO_INTF2_STATUS RO 0x0 31:1 RESERVED Reserved.
0 VC2_MODE_MATCH Asserted when the input data resolution is matching with the WIDTH and HEIGHT_F0/HEIGHT_F1 registers for video streaming interface 2.
0x153 VIDEO_INTF3_STATUS RO 0x0 31:1 RESERVED Reserved.
0 VC3_MODE_MATCH Asserted when the input data resolution is matching with the WIDTH and HEIGHT_F0/HEIGHT_F1 registers for video streaming interface 3.
0x154 – 0x15F RESERVED N/A N/A 31:0 RESERVED Reserved.
0x160 VIDEO_INTF0_WIDTH RW 0x0 31:16 RESERVED Reserved.
15:0 VC0_WIDTH Specifies the active video width(in pixel unit) for video streaming interface 0.
0x161 VIDEO_INTF1_WIDTH RW 0x0 31:16 RESERVED Reserved.
15:0 VC1_WIDTH Specifies the active video width (in pixel unit) for video streaming interface 1.
0x162 VIDEO_INTF2_WIDTH RW 0x0 31:16 RESERVED Reserved.
15:0 VC2_WIDTH Specifies the active video width (in pixel unit) for video streaming interface 2.
0x163 VIDEO_INTF3_WIDTH RW 0x0 31:16 RESERVED Reserved.
15:0 VC3_WIDTH Specifies the active video width (in pixel unit) for video streaming interface 3.
0x164 – 0x16F RESERVED N/A N/A 31:0 RESERVED Reserved.
0x170 VIDEO_INTF0_HEIGHT_F0 RW 0x0 31:16 RESERVED Reserved.
15:0 VC0_HEIGHT_F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 0.
0x171 VIDEO_INTF1_HEIGHT_F0 RW 0x0 31:16 RESERVED Reserved.
15:0 VC1_HEIGHT_F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 1.
0x172 VIDEO_INTF2_HEIGHT_F0 RW 0x0 31:16 RESERVED Reserved.
15:0 VC2_HEIGHT_F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 2.
0x173 VIDEO_INTF3_HEIGHT_F0 RW 0x0 31:16 RESERVED Reserved.
15:0 VC3_HEIGHT_F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 3.
0x74 – 0x7F RESERVED N/A N/A 31:0 RESERVED Reserved.
0x180 VIDEO_INTF0_HEIGHT_F1 RW 0x0 31:16 RESERVED Reserved.
15:0 VC0_HEIGHT_F1 Specifies the active video height (in line unit) interlaced video field 1 for video streaming interface 0.
0x181 VIDEO_INTF1_HEIGHT_F1 RW 0x0 31:16 RESERVED Reserved.
15:0 VC1_HEIGHT_F1 Specifies the active video height (in line unit) interlaced video field 1 for video streaming interface 1.
0x182 VIDEO_INTF2_HEIGHT_F1 RW 0x0 31:16 RESERVED Reserved.
15:0 VC2_HEIGHT_F1 Specifies the active video height (in line unit) interlaced video field 1 for video streaming interface 2.
0x183 VIDEO_INTF3_HEIGHT_F1 RW 0x0 31:16 RESERVED Reserved.
15:0 VC3_HEIGHT_F1 Specifies the active video height (in line unit) interlaced video field 1 for video streaming interface 3.
0x184 – 0x18F RESERVED N/A N/A 31:0 RESERVED Reserved.
0x190 VIDEO_INTF0_LINE_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC0_LINE_BLANKING Specifies the line blanking in pixels for video streaming interface 0.
0x191 VIDEO_INTF1_LINE_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC1_LINE_BLANKING Specifies the line blanking in pixels for video streaming interface 1.
0x192 VIDEO_INTF2_LINE_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC2_LINE_BLANKING Specifies the line blanking in pixels for video streaming interface 2.
0x193 VIDEO_INTF3_LINE_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC3_LINE_BLANKING Specifies the line blanking in pixels for video streaming interface 3.
0x194 – 0x19F RESERVED N/A N/A 31:0 RESERVED Reserved.
0x1A0 VIDEO_INTF0_FRAME_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC0_FRAME_BLANKING Specifies the frame blanking in lines for video streaming interface 0.
0x1A1 VIDEO_INTF1_FRAME_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC1_FRAME_BLANKING Specifies the frame blanking in lines for video streaming interface 1.
0x1A2 VIDEO_INTF2_FRAME_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC2_FRAME_BLANKING Specifies the frame blanking in lines for video streaming interface 2.
0x1A3 VIDEO_INTF3_FRAME_BLANK RW 0x0 31:16 RESERVED Reserved.
15:0 VC3_FRAME_BLANKING Specifies the frame blanking in lines for video streaming interface 3.
0x1A4 – 0x1AF RESERVED N/A N/A 31:0 RESERVED Reserved.
0x1B0 VIDEO_INTF0_CONTROL RW 0x0 31:2 RESERVED Reserved.
1 VC0_LINE_FRAMING_PKT_ENABLE When set, enables insertion of MIPI line start and line end short packets for video streaming interface 0.
0 INTERLACED Specifies whether video is interlaced for video streaming interface 0.
0x1B1 VIDEO_INTF1_CONTROL RW 0x0 31:2 RESERVED Reserved.
1 VC1_LINE_FRAMING_PKT_ENABLE When set, enables insertion of MIPI line start and line end short packets for video streaming interface 1.
0 INTERLACED Specifies whether video is interlaced for video streaming interface 1.
0x1B2 VIDEO_INTF2_CONTROL RW 0x0 31:2 RESERVED Reserved.
1 VC2_LINE_FRAMING_PKT_ENABLE When set, enables insertion of MIPI line start and line end short packets for video streaming interface 2.
0 INTERLACED Specifies whether video is interlaced for video streaming interface 2.
0x1B3 VIDEO_INTF3_CONTROL RW 0x0 31:2 RESERVED Reserved.
1 VC3_LINE_FRAMING_PKT_ENABLE When set, enables insertion of MIPI line start and line end short packets for video streaming interface 3.
0 INTERLACED Specifies whether video is interlaced for video streaming interface 3.
0x1B4 – 0xFF RESERVED N/A N/A 31:0 RESERVED Reserved.
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