MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 7/23/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

2.3.5. Transmitter PPI Signals

The interface between the Intel MIPI D-PHY IP and the MIPI CSI-2 Intel® FPGA IP uses the PPI defined in the MIPI D-PHY standards. This interface carries the outgoing data stream from the CSI-2 Transmitter that the D-PHY IP processes.
Table 13.  Transmitter PPI Signals
Signal Width Direction Description
Clock Lane High Speed Transmit <ppi_width>=16
tx_word_clk_hs_ck 1 Input Refer to MIPI D-PHY specification version 2.5: Figures 92-94 Example High-Speed Transmission from the Master Side: 8-/16-/32-Bit Bus Width.
tx_data_width_hs_ck 2 Output
tx_data_hs_ck ppi_width Output
tx_valid_hs_ck ppi_width/8 Output
tx_data_transfer_en_hs_ck 1 Output
tx_request_hs_ck 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 90, Example High Speed Clock Enable, LP Mode. Figure 121 High Speed Transmission and Reception with HS-Idle Function.
tx_ready_hs_ck 1 Input
tx_eq_active_hs_ck 1 Output Refer to MIPI D-PHY specification version 2.5 Table 50.
tx_eq_level_hs_ck 1 Output
tx_skew_cal_hs_ck 1 Output Skew calibration. Implementation-specific how the system responds to this condition. Refer to MIPI D-PHY specification version 2.5: Figure 119. Skew Calibration, LP Mode.
tx_alternate_cal_hs_ck 1 Output
Data Lane High Speed Transmit <lane>=0-7; <ppi_width>=16
tx_word_clk_hs_d<lane> 1 Input Refer to MIPI D-PHY specification version 2.5: Figures 92-94 Example High-Speed Transmission from the Master Side: 8-/16-/32-Bit Bus Width.
tx_data_width_hs_d<lane> 2 Output
tx_data_hs_d<lane> ppi_width Output
tx_valid_hs_d<lane> ppi_width/8 Output
tx_data_transfer_en_hs_d<lane> 1 Output
tx_request_hs_d<lane> 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 90, Example High Speed Clock Enable, LP Mode. Figure 121 High Speed Transmission and Reception with HS-Idle Function.
tx_ready_hs_d<lane> 1 Input
tx_eq_active_hs_d<lane> 1 Output Refer to MIPI D-PHY specification version 2.5 Table 50.
tx_eq_level_hs_d<lane> 1 Output
tx_skew_cal_hs_d<lane> 1 Output Calibration. Implementation-specific how the system responds to this condition. Refer to MIPI D-PHY specification version 2.5: Figure 119. Skew Calibration, LP Mode.
tx_alternate_cal_hs_d<lane> 1 Output
Clock Lane Escape Mode Transmit (LPDT= low-power data transmission, ULPS = Sleep Mode)
tx_clk_esc_ck 1 Input Escape mode signals – Refer to MIPI D-PHY specification version 2.5 Table 50.
tx_request_esc_ck 1 Output
tx_request_type_esc_ck 4 Output
tx_lpdt_esc_ck 1 Output
tx_ulps_exit_ck 1 Output
tx_ulps_esc_ck 1 Output
tx_trigger_esc_ck 4 Output
tx_data_esc_ck 8 Output
tx_valid_esc_ck 1 Output
tx_ready_esc_ck 1 Input
Data Lane Escape Mode Transmit (LPDT= low-power data transmission, ULPS = Sleep Mode). <lane>=0-7
tx_clk_esc_d<lane> 1 Input Escape mode signals – Refer to MIPI D-PHY specification version 2.5 Table 50.
tx_request_esc_d<lane> 1 Output
tx_request_type_esc_d<lane> 4 Output
tx_lpdt_esc_d<lane> 1 Output
tx_ulps_exit_d<lane> 1 Output
tx_ulps_esc_d<lane> 1 Output
tx_trigger_esc_d<lane> 4 Output
tx_data_esc_d<lane> 8 Output
tx_valid_esc_d<lane> 1 Output
tx_ready_esc_d<lane> 1 Input
Clock Lane Control
turn_request_ck 1 Output Clock lane direction signals – Refer to MIPI D-PHY specification version 2.5 Table 50.
direction_ck 1 Input
turn_disable_ck 1 Output
force_rx_mode_ck 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 86. Master PHY Enable, LP Mode.
force_tx_stop_mode_ck 1 Output
stop_state_ck 1 Input
enable_ck 1 Output
alp_mode_ck 1 Output Alternate Low Power Mode Selection - Refer to MIPI D-PHY specification version 2.5 Table 50.
tx_ulps_clk_ck 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 114. Example Clock Lane ULPS Entry and Exit, LP Mode.
rx_ulps_clk_not_ck 1 Input
ulps_active_not_ck 1 Input
tx_hsidle_clk_hs_ck 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 121. HS Transmission and Reception with HS-IDLE Function.
tx_hsidle_clk_ready_hs_ck 1 Input
Data Lane Control<lane>=0-7
turn_request_d<lane> 1 Output Data lane direction signals – Refer to MIPI D-PHY specification version 2.5 Table 50.
direction_d<lane> 1 Input
turn_disable_d<lane> 1 Output
force_rx_mode_d<lane> 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 86. Master PHY Enable, LP Mode.
force_tx_stop_mode_d<lane> 1 Output
stop_state_d<lane> 1 Input
enable_d<lane> 1 Output
alp_mode_d<lane> 1 Output Alternate Low Power Mode Selection - Refer to MIPI D-PHY specification version 2.5 Table 50.
tx_ulps_clk_d<lane> 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 114. Example Clock Lane ULPS Entry and Exit, LP Mode.
rx_ulps_clk_not_d<lane> 1 Input
ulps_active_not_d<lane> 1 Input
tx_hsidle_clk_hs_d<lane> 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 121. HS Transmission and Reception with HS-IDLE Function.
tx_hsidle_clk_ready_hs_d<lane> 1 Input
Level Two Title