MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 7/23/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

2.3.4. Receiver AXI4-Stream Output Passthrough Interface

The MIPI CSI-2 IP uses this interface when in passthrough mode. It carries the MIPI CSI-2 packets recovered from the external MIPI input, as defined by the MIPI CSI-2 specification low-level protocol. This interface allows retransmission or custom processing of the received MIPI CSI-2 packets. For example in bridging applications where the IP combines multiple incoming CSI-2 streams into a single outgoing CSI-2 stream.

The IP combines MIPI CSI-2 packets from multiple lanes, if configured, but performs no further processing. The packets have packet header followed by payload and checksum for long packets.

The IP includes a single AXI4-Stream output interface, containing data from all virtual channels. According to your system requirements you can process this data as a combined stream or decode it further based on the virtual channel ID in the packet headers.

Table 12.  Receiver AXI4-Stream Output Passthrough Interface Signalschannel_width = PPI_data_width × lane_count
Signal Width Direction Description
axi4s_mipi_out_tdata channel_width Output Packet data
axi4s_mipi_out_tkeep channel_width ÷ 8 Output Packet tkeep
axi4s_mipi_out_tvalid 1 Output Ppacket data_valid
axi4s_mipi_out_tuser 1 Output

Bit0: AXI4-Stream start of packet

0 = Not start of packet

1 = Start of packet
axi4s_mipi_out_tlast 1 Output AXI4-Stream end of packet
axi4s_mipi_out_tready 1 Input AXI4-Stream data ready
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