MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 7/23/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems

Figure 2. Files Generated for IP and Platform Designer Systems
Table 18.  IP and Platform Designer Simulation Files
File Name Description
<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
<my_ip>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<my_ip>.qgsimc Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP. This comparison determines if Platform Designer can skip regeneration of the HDL.
<my_ip>.qgsynth Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP. This comparison determines if Platform Designer can skip regeneration of the HDL.
<my_ip>.qip Contains all the required information about the IP component to integrate and compile the IP component in the Quartus® Prime software.
<my_ip>.csv Contains information about the upgrade status of the IP component.

<my_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Block Diagram Files (.bdf).
<my_ip<>.spd Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.
<my_ip>_bb.v Use the Verilog black box (_bb.v) file as an empty module declaration for use as a black box.
<my_ip>_inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<my_ip>.v <my_ip>.vhd HDL files that instantiate each submodule or child IP for synthesis or simulation.
sim/mentor/ Contains a Questa* Intel® FPGA Edition script msim_setup.tcl to set up and run a simulation.
sim/aldec/ Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

sim/synopsys/vcsmx/

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX® simulation.

sim/xcelium/ Contains a shell script xcelium_setup.sh and other setup files to set up and run a Xcelium simulation.
sim/common/ Contains a set of Tcl files, <simulator>_files.tcl, which provide all design related simulation information required by a corresponding simulation script. The Tcl file contains designs from current system-level hierarchy, and references to sub-systems and IP components.
<IP submodule>/ For each generated IP submodule directory, Platform Designer generates /synth and /sim sub-directories under IP-specific directories..
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