MIPI CSI-2 Intel® FPGA IP User Guide

ID 813926
Date 7/23/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.1. Receiver PPI Signals

The interface between the MIPI CSI-2 Intel® FPGA IP and the Intel MIPI D-PHY IP uses the PPI defined in the MIPI D-PHY and CSI-2 standards. This interface carries the received MIPI data stream to be decoded by the CSI-2 Receiver.
Table 8.  Receiver PPI Signals
Signal Width Direction Description
Clock Lane High Speed Receive <ppi_width>=16
rx_data_width_hs_ck 2 Output Refer to MIPI D-PHY specification version 2.5: Figure 95 and 97, 101 High Speed Receive on Slave Side, 8/16-bit Bus, LP Mode.
rx_data_hs_ck ppi_width Input
rx_valid_hs_ck ppi_width/8 Input
rx_active_hs_ck 1 Input
rx_sync_hs_ck 1 Input
rx_clk_active_hs_ck 1 Input Refer to MIPI D-PHY specification version 2.5: Figure 90, Example High Speed Clock Enable, LP Mode. Figure 121 High Speed Transmission and Reception with HS-Idle Function.
rx_skew_cal_hs_ck 1 Input Calibration. Implementation-specific how the system responds to this condition. Refer to MIPI D-PHY specification version 2.5: Figure 119. Skew Calibration, LP Mode.
rx_alternate_cal_hs_ck 1 Input
rx_error_cal_hs_ck 1 Input
Data Lane High Speed Receive <lane>=0-7; <ppi_width>=16
rx_srst_n_d<lane> 1 Input Synchronous reset from Intel MIPI RX D-PHY.
rx_word_clk_hs_ d<lane> 1 Input Refer to MIPI D-PHY specification version 2.5: Figure 95 and 97, 101 High Speed Receive on Slave Side, 8/16-bit Bus, LP Mode.
rx_data_width_hs_ d<lane> 2 Output
rx_data_hs_ d<lane> ppi_width Input
rx_valid_hs_ d<lane> ppi_width/8 Input
rx_active_hs_ d<lane> 1 Input
rx_sync_hs_ d<lane> 1 Input
rx_clk_active_hs_ d<lane> 1 Input Refer to MIPI D-PHY specification version 2.5: Figure 90 Example High Speed Clock Enable, LP Mode. Figure 125 High Speed Transmission and Reception with HS-Idle Function.
rx_skew_cal_hs_ d<lane> 1 Input Calibration. Implementation-specific how the system responds to this condition. Refer to MIPI D-PHY specification version 2.5: Figure 119. Skew Calibration, LP Mode.
rx_alternate_cal_hs_ d<lane> 1 Input
rx_error_cal_hs_ d<lane> 1 Input
Clock Lane Escape Mode Receive (LPDT = low=power data transmission, ULPS = Sleep Mode)
rx_clk_esc_ck 1 Input For (LPDT. Required for USL control data communication. Refer to MIPI D-PHY specification version 2.5: Figure 107 Example Low-Power Data Reception, LP Mode.
rx_lpdt_esc_ck 1 Input
rx_data_esc_ck 8 Input
rx_valid_esc_ck 1 Input
rx_trigger_esc_ck 4 Input For LPDT. The IP ignores any bit received after a Trigger Command (i.e., Reset Trigger) and before the Lines go to the Stop state. Refer to MIPI D-PHY specification version 2.5: Figure 110-112.
rx_ulps_esc_ck 1 Input For ULPS and used with ulps_active_not_ck. Refer to MIPI D-PHY specification version 2.5: Figure 116 Example Data Lane ULPS Entry and Exit, LP Mode.
Data Lane Escape Mode Receive (LPDT = low-power data transmission, ULPS = Sleep Mode). <lane>=0-7
rx_clk_esc_d<lane> 1 Input For LPDT. Required for USL control data communication. Refer to MIPI D-PHY specification version 2.5: Figure 107 Example Low-Power Data Reception, LP Mode.
rx_lpdt_esc_d<lane> 1 Input
rx_data_esc_d<lane> 8 Input
rx_valid_esc_d<lane> 1 Input
rx_trigger_esc_d<lane> 4 Input For LPDT. The IP ignores any bit received after a Trigger Command (i.e., reset trigger) and before the Lines go to the Stop state. Refer to MIPI D-PHY specification version 2.5: Figure 110-112.
rx_ulps_esc_d<lane> 1 Input For ULPS and used with ulps_active_not_ck. Refer to MIPI D-PHY specification version 2.5: Figure 116 Example Data Lane ULPS Entry and Exit, LP Mode.
Clock Lane Control
direction_ck 1 Input

Indicates the current direction of Lane.

0 = Transmit mode.

1 = Receive mode.

force_rx_mode_ck 1 Output

For Transmit:

Refer to MIPI D-PHY specification version 2.5: Figure 86. Master PHY Enable, LP Mode.

For Receive:

Refer to MIPI D-PHY specification version 2.5: Figure 88. Example Slave PHY Enable, LP Mode.

force_tx_stop_mode_ck 1 Output
stop_state_ck 1 Input
enable_ck 1 Output
alp_mode_ck 1 Output

Alternate Low Power Mode Selection.

0 = LP mode.

1 = ALP mode.

tx_ulps_clk_ck 1 Output Refer to MIPI D-PHY specification version2.5: Figure 114. Example Clock Lane ULPS Entry and Exit, LP Mode.
rx_ulps_clk_not_ck 1 Input
ulps_active_not_ck 1 Input
tx_hsidle_clk_hs_ck 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 121. HS Transmission and Reception with HS-IDLE Function.
tx_hsidle_clk_ready_hs_ck 1 Input
Data Lane Control<lane>=0-7
direction_d<lane> 1 Input

Indicates the current direction of Lane.

0 = Transmit mode.

1 = Receive mode.

force_rx_mode_d<lane> 1 Output

For Transmit:

Refer to MIPI D-PHY specification version 2.5: Figure 86. Master PHY Enable, LP Mode.

For Receive:

Refer to MIPI D-PHY specification version 2.5: Figure 88. Example Slave PHY Enable, LP Mode.

force_tx_stop_mode_d<lane> 1 Output
stop_state_d<lane> 1 Input
enable_d<lane> 1 Output
alp_mode_d<lane> 1 Output

Alternate Low Power Mode Selection.

0 = LP mode.

1 = ALP mode.

tx_ulps_clk_d<lane> 1 Output Refer to D-PHY specification version 2.5: Figure 114. Example Clock Lane ULPS Entry and Exit, LP Mode.
rx_ulps_clk_not_d<lane> 1 Input
ulps_active_not_d<lane> 1 Input
tx_hsidle_clk_hs_d<lane> 1 Output Refer to MIPI D-PHY specification version 2.5: Figure 121. HS Transmission and Reception with HS-IDLE Function.
tx_hsidle_clk_ready_hs_d<lane> 1 Input
Clock Lane Error Input
i_err_sot_hs_ck 1 Input Start-of-transmission error.
i_err_sot_sync_hs 1 Input Start-of-transmission synchronization error.
i_err_esc_ck 1 Input Escape entry error.
i_err_sync_ck 1 Input Low-power data transmission synchronization error.
i_err_control_ck 1 Input Control error.
i_err_contention_lp0_ck 1 Input LP0 Contention error.
i_err_contention_lp1_ck 1 Input LP1 Contention error.
Data Lane Error Input<lane>=0-7
i_err_sot_hs_d<lane> 1 Input Start-of-transmission error.
i_err_sot_sync_d<lane> 1 Input Start-of-transmission synchronization error.
i_err_esc_d<lane> 1 Input Escape entry error.
i_err_sync_d<lane> 1 Input Low-power data transmission synchronization error.
i_err_control_d<lane> 1 Input Control error.
i_err_contention_lp0_d<lane> 1 Input LP0 Contention error.
i_err_contention_lp1_d<lane> 1 Input LP1 Contention error.
Clock Lane Error Passthrough Output
o_err_sot_hs_ck 1 Input Start-of-transmission error.
o_err_sot_sync_hs 1 Input Start-of-transmission synchronization error.
o_err_esc_ck 1 Input Escape entry error.
o_err_sync_ck 1 Input Low-power data transmission synchronization error.
o_err_control_ck 1 Input Control error.
o_err_contention_lp0_ck 1 Input LP0 contention error.
o_err_contention_lp1_ck 1 Input LP1 contention error.
Data Lane Error Passthrough Output<lane>=0-7
o_err_sot_hs_d<lane> 1 Input Start-of-transmission error.
o_err_sot_sync_d<lane> 1 Input Start-of-transmission synchronization error.
o_err_esc_d<lane> 1 Input Escape ntry error.
o_err_sync_d<lane> 1 Input Low-power data transmission synchronization error.
o_err_control_d<lane> 1 Input Control error.
o_err_contention_lp0_d<lane> 1 Input LP0 Contention error.
o_err_contention_lp1_d<lane> 1 Input LP1 Contention error.