MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

2.3.3. Receiver AXI4-Stream Output Video Interface Signals

These MIPI CSI-2 IP signals follow the Intel Streaming Video protocol (full variant). For more information about this protocol and rules for pixel formatting see the Intel FPGA Streaming Video Protocol Specification .

Equation 1. Video Interface Bit Widths

Table 10.  Examples for Video Interface Bit Widths
Data Type bits_per_color_plane number_of_color_planes
YUV422 8-bit 8 2
RGB565 6 3
RAW10 10 1
Table 11.  Receiver AXI4-Stream Output Video Interface Signals VC indicates virtual channel ID, between 0 and 3 according to IP configuration.
Signal Width Direction Description
axi4s_vid_out_VC_tdata P Output AXI4-Stream data out.
axi4s_vid_out_VC_tvalid 1 Output AXI4-Stream data valid.
axi4s_vid_out_VC_tuser Q Output

Bit 0: AXI4-Stream start of video frame.

0 = Not start of field

1 = Start of field

Bit 1: AXI4-Stream meta or data packet.

0 = Video packet

1 = Metapacket

Bit Q-1:2: Unused
axi4s_vid_out_VC_tlast 1 Output AXI4-Stream end of packet.
axi4s_vid_out_VC_tready 1 Input AXI4-Stream data ready.
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