MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

6.1. CSI-2 Receiver Register Map

Base address (control_address[9:8]) 0x0 accesses the MIPI CSI-2 receiver control and status registers. Base 0x1 accesses the CV2AXI registers.
Table 26.  Register Access Codes
Code Description
RW Read and write.
RO Read only.
RW1C Read, write and clear. Your application writes 1 to the register bit(s) to invoke a defined instruction. The IP clears the bit(s) on running instructions.
Table 27.  CSI-2 Receiver IP Registers
Address [9:0] Register Access Default Bit Bit Name Description
0x000 CORE_STATUS RO 0x0 31:3 RESERVED Reserved.
LANES-1 2:0 MAXIMUM_LANES Number of D-PHY lanes configured during IP generation minus 1. For example, 4 lanes = 3.
0x001 – 0x003 RESERVED N/A N/A N/A RESERVED Reserved.
0x004 GENERIC_SHORT_PACKET RO 0x0 31:26 RESERVED Reserved.
25:8 DATA 16 bits payload data of the generic short packet.
7:6 VIRTUAL_CHANNEL Virtual channel identifier.
5:0 DATA_TYPE Generic short packet code.
0x05 – 0x0F RESERVED N/A N/A N/A RESERVED Reserved.
0x010 VC0_IMAGE_INFO RO 0x0 31:6 RESERVED Reserved.
5:0 VC0_VIDEO_DATA_TYPE Data type of current packet (0x18 and above) received on VC0.
0x011 VC1_IMAGE_INFO RO 0x0 31:6 RESERVED Reserved.
5:0 VC1_VIDEO_DATA_TYPE Data type of current packet (0x18 and above) received on VC1.
0x012 VC2_IMAGE_INFO RO 0x0 31:6 RESERVED Reserved.
5:0 VC2_VIDEO_DATA_TYPE Data type of current packet (0x18 and above) received on VC2.
0x013 VC3_IMAGE_INFO RO 0x0 31:6 RESERVED Reserved.
5:0 VC3_VIDEO_DATA_TYPE Data type of current packet (0x18 and above) received on VC3.
0x014 – 0x01F VC<ch>_IMAGE_INFO RO 0x0 31:6 RESERVED Reserved.
5:0 VC<ch>_VIDEO_DATA_TYPE

Data type of current packet (0x18 and above) received on VC<ch>.

<ch>: 4-15

0x020 – 0x050 RESERVED N/A N/A N/A RESERVED Reserved.
0x051 DATA_TYPE_ERROR_IRQ_STATUS RW1C 0x0 31:16 RESERVED Reserved.
15:1 VC<ch>_DT_ERROR Interrupt status registers for data type error indicator on VC1 through VC15.
0 VC0_DT_ERROR Interrupt status register. Asserts when a packet header is decoded with an unrecognized or not implemented ID on VC0.
0x052 FRAME_SYNC_ERROR_IRQ_STATUS RW1C 0x0 31:16 RESERVED Reserved.
15:1 VC<ch>_FRAME_SYNC_ERR Interrupt status registers for frame sync error indicator on VC1 through VC15.
0 VC0_FRAME_SYNC_ERR Interrupt status register. Asserts when an FE is not paired with a FS on VC0.
0x053 FRAME_DATA_ERROR_IRQ_STATUS RW1C 0x0 31:16 RESERVED Reserved.
15:1 VC<ch>_FRAME_DATA_ERR Interrupt status registers for frame CRC error indicator on VC1 through VC15.
0 VC0_FRAME_DATA_ERR Interrupt status register. Asserts when the data payload received between FS and FE contains CRC errors on VC0.
0x054 ECC_1BIT_ERROR_IRQ_STATUS RW1C 0x0 31:16 RESERVED Reserved.
15:1 VC<ch>_ECC_1BIT_ERR Interrupt status registers for ECC single bit error indicator on VC1 through VC15.
0 VC0_ECC_1BIT_ERR Interrupt status register. Asserts when the IP calculates an ECC syndrome and it detects and corrects a single bit error in the packet header on VC0.
0x055 ECC_2BIT_ERROR_IRQ_STATUS RW1C 0x0 31:16 RESERVED Reserved.
15:1 VC<ch>_ECC_2BIT_ERR Interrupt status registers asserted when the IP detects an uncorrectable 2-bit ECC error on VC1 through 15.
0 VC0_ECC_2BIT_ERR Interrupt status register. Asserts when the IP calculates an ECC syndromeand detects an uncorrectable 2-bit error in the received packet header on VC0.
0x056 – 0x06F RESERVED N/A N/A N/A RESERVED Reserved.
0x070 CSI2_RX_INTERRUPT_MASK_ENABLE RW 0x0 31:6 RESERVED Reserved.
5 IRQ_EN_ECC_2BIT_ERR Interrupt enable registers allow you to selectively generate an interrupt at the output port for each error bit in the registers 0x51 through 0x55. Set to 0 to disable the interrupt.
4 IRQ_EN_ECC_1BIT_ERR
3 IRQ_EN_FRAME_DATA_ERR
2 IRQ_EN_FRAME_SYNC_ERR
1 IRQ_EN_DATA_TYPE_ERR
0 RESERVED Reserved.
0x071 – 0x14F RESERVED N/A N/A N/A RESERVED Reserved.
0x150 VIDEO_INTF0_STATUS RO 0x0 31:2 RESERVED Reserved.
1 VC0_INTERLACED Interlaced bit of video streaming interface 0. When asserted, the input video stream is interlaced. Otherwise, the input video stream is progressive.
0 RESERVED Reserved.
0x151 VIDEO_INTF1_STATUS RO 0x0 31:2 RESERVED Reserved.
1 VC1_INTERLACED Interlaced bit of video streaming interface 1. When asserted, the input video stream is interlaced. Otherwise, the input video stream is progressive.
0 RESERVED Reserved.
0x152 VIDEO_INTF2_STATUS RO 0x0 31:2 RESERVED Reserved.
  1 VC2_INTERLACED Interlaced bit of video streaming interface 2. When asserted, the input video stream is interlaced. Otherwise, the input video stream is progressive.
  0 RESERVED Reserved.
0x153 VIDEO_INTF3_STATUS RO 0x0 31:2 RESERVED Reserved.
1 VC3_INTERLACED Interlaced bit of video streaming interface 3. When asserted, the input video stream is interlaced. Otherwise, the input video stream is progressive.
0 RESERVED Reserved
0x154 – 0x15F RESERVED N/A N/A N/A RESERVED Reserved.
0x160 VIDEO_INTF0_WIDTH RO 0x0 31:16 RESERVED Reserved.
15:0 VC0_WIDTH Specifies the active video width (in pixel unit) for video streaming interface 0.
0x161 VIDEO_INTF1_WIDTH RO 0x0 31:16 RESERVED Reserved.
15:0 VC1_WIDTH Specifies the active video width (in pixel unit) for video streaming interface 1.
0x162 VIDEO_INTF2_WIDTH RO 0x0 31:16 RESERVED Reserved.
15:0 VC2_WIDTH Specifies the active video width (in pixel unit) for video streaming interface 2.
0x163 VIDEO_INTF3_WIDTH RO 0x0 31:16 RESERVED Reserved.
15:0 VC3_WIDTH Specifies the active video width (in pixel unit) for video streaming interface 3.
0x164 – 0x16F RESERVED N/A N/A N/A RESERVED Reserved.
0x170 VIDEO_INTF0_HEIGHT_F0 RO 0x0 31:16 RESERVED Reserved.
15:0 VC0_HEIGHT_F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 0.
0x171 VIDEO_INTF1_HEIGHT_F0 RO 0x0 31:16 RESERVED Reserved.
15:0 VC1_HEIGHT F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 1.
0x172 VIDEO_INTF2_HEIGHT_F0 RO 0x0 31:16 RESERVED Reserved.
15:0 VC2_HEIGHT F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 2.
0x173 VIDEO_INTF3_HEIGHT_F0 RO 0x0 31:16 RESERVED Reserved.
15:0 VC3_HEIGHT F0 Specifies the active video height (in line unit) of progressive video or interlaced video field 0 for video streaming interface 3.
0x174 – 0x17F RESERVED N/A N/A N/A RESERVED Reserved.
0x180 VIDEO_INTF0_HEIGHT_F1 RO 0x0 31:16 RESERVED Reserved.
15:0 VC0_HEIGHT_F1 Specifies the active video height (in line unit) for interlaced video field 1 for video streaming interface 0.
0x181 VIDEO_INTF1_HEIGHT_F1 RO 0x0 31:16 RESERVED Reserved.
15:0 VC1_HEIGHT F1 Specifies the active video height (in line unit) for interlaced video field 1 for video streaming interface 1.
0x182 VIDEO_INTF2_HEIGHT_F1 RO 0x0 31:16 RESERVED Reserved.
15:0 VC2_HEIGHT F1 Specifies the active video height (in line unit) for interlaced video field 1 for video streaming interface 2.
0x183 VIDEO_INTF3_HEIGHT_F1 RO 0x0 31:16 RESERVED Reserved.
15:0 VC3_HEIGHT F1 Specifies the active video height (in line unit) for interlaced video field 1 for video streaming interface 3.
0x184 – 0x18F RESERVED N/A N/A N/A RESERVED Reserved.
0x190 VIDEO_INTF0_COLOR_PATTERN RO 0x0 31:13 RESERVED Reserved
0xF 12:9 VC0_COLOR_SPACE

Specifies the color space for video streaming interface 0.

1: YUV

2:4: Reserved

7-15: Reserved
0x0 8:7 VC0_COSITE

Specifies the co-siting of the chroma samples for video streaming interface 0.

0: Reserved.

1: Top and center (ie. YUV420 8/10-bit Chroma Shifted Pixel Sampling).

2: Reserved.

3: Center and center (YUV420 8/10-bit).
0x1 6:5 VC0_SUBSAMPLING

Specifies the chroma sampling for video streaming interface 0.

0: 420.

1: Reserved.

2: 422.

3: 444.
0x0 4:0 VC0_BIT_WIDTH_-1 Specifies the bit width – 1 for video streaming interface 0. I.e., value of 5’d23 indicates bit width of 24.
0x191 VIDEO_INTF1_COLOR_PATTERN RO 0x0 31:13 RESERVED Reserved.
0xF 12:9 VC1_COLOR SPACE

Specifies the color space for video streaming interface 1.

0: RGB

1-4: Reserved

5: RAW

6: RGB565

7: YUV

8: YUVlegacy

9-15: Reserved
0x0 8:7 VC1_COSITE

Specifies the co-siting of the chroma samples for video streaming interface 1.

0: Reserved

1: Top and center (ie. YUV4208/10-bit Chroma Shifted Pixel Sampling)

2: Reserved

3: Center and center (YUV420 8/10-bit)
0x1 6:5 VC1_SUBSAMPLING

Specifies the chroma sampling for video streaming interface 1.

0: 420

1: Reserved

2: 422

3: 444
0x0 4:0 VC1_BIT WIDTH MINUS 1 Specifies the bit width – 1 for video streaming interface 1. I.e., value of 5’d23 indicates bit width of 24.
0x192 VIDEO_INTF2_COLOR_PATTERN RO 0x0 31:13 RESERVED Reserved.
0xF 12:9 VC2_COLOR SPACE

Specifies the color space for video streaming interface 2.

0: RGB

1-4: Reserved

5: RAW

6: RGB565

7: YUV

8: YUVlegacy

9-15: Reserved

0x0 8:7 VC2_COSITE

Specifies the co-siting of the chroma samples for video streaming interface 2.

0: Reserved

1: Top and center (ie. YUV4208/10-bit Chroma Shifted Pixel Sampling)

2: Reserved

3: Center and center (YUV420 8/10-bit)

0x1 6:5 VC2_SUBSAMPLING

Specifies the chroma sampling for video streaming interface 2.

0: 420

1: Reserved

2: 422

3: 444
0x0 4:0 VC2_BIT WIDTH MINUS 1 Specifies the bit width – 1 for video streaming interface 2. I.e., value of 5’d23 indicates bit width of 24.
0x193 VIDEO_INTF3_COLOR_PATTERN RO 0x0 31:13 RESERVED Reserved.
0xF 12:9 VC3_COLOR SPACE

Specifies the color space for video streaming interface 3.

0: RGB

1-4: Reserved

5: RAW

6: RGB565

7: YUV

8: YUVlegacy

9-15: Reserved

0x0 8:7 VC3_COSITE

Specifies the co-siting of the chroma samples for video streaming interface 3.

0: Reserved

1: Top and center (ie. YUV4208/10-bit Chroma Shifted Pixel Sampling)

2: Reserved

3: Center and center (YUV420 8/10-bit)

0x1 6:5 VC3_SUBSAMPLING

Specifies the chroma sampling for video streaming interface 3.

0: 420

1: Reserved

2: 422

3: 444
0x0 4:0 VC3_BIT WIDTH MINUS 1 Specifies the bit width – 1 for video streaming interface 3. I.e., value of 5’d23 indicates bit width of 24.
0x194 – 0x1AF RESERVED N/A N/A N/A RESERVED Reserved.
0x1B0 CORE_STATUS_IRQ_STATUS RW1C 0x0 31:1 RESERVED Reserved.
0 VIDEO_INTF<ch>_STABLE Stable bit of video streaming interface 0 to 3. When asserted, the IP detects a a consistent width and height on the input video stream.
0x1B1 – 0x1B3 RESERVED N/A N/A N/A RESERVED Reserved.
0x1B4 CV2AXI_INTERRUPT_MASK_ENABLE RW 0x0 31:4 RESERVED Reserved.
3:0 IRQ_EN_CORE_STATUS_INTF0 Interrupt enable registers allow you to selectively generate an interrupt at the output port for each error bit in the registers 0x1B0. Set to 0 to disable the interrupts.
0x1B5 – 0x3FF RESERVED N/A N/A N/A RESERVED Reserved.
Level Two Title