MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 7/23/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interfaces 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resources 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interfaces
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

4.3.5. Limitations and Known Issues

The MIPI CSI-2 Intel® FPGA IP supports the mandatory feature set of the MIPI CSI-2 specification version 3.0 and the MIPI D-PHY specification version 2.5.

Altera recommends that you read the information in the MIPI D-PHY Intel® FPGA IP User Guide, which describes the supported features in Agilex™ 5 FPGAs and the MIPI D-PHY IP. For a successful implementation, follow the guidance on D-PHY pin locations .

In this release, the MIPI CSI-2 Intel® FPGA IP provides support for between one and four virtual channels. The IP does not support 4-bit virtual channel IDs (VCIDs) using CSI-2 virtual channel extension (VCX) signaling. The IP does not process the additional 12 virtual channels added by VCX (VCIDs 4 to 15) and drops any video data using these extended VCIDs. Packet headers must contain 6-bit ECC and 2-bit VC. The receiver supports up to four virtual channels in all data types except YUV420 formats, where one virtual channel only is supported.

Video line length and RX AXI-S line blanking must be an integer multiple of the CSI-2 data type packing multiple. For example, multiples of four pixels for RAW10, where four 10-bit pixels are packed into five bytes. The MIPI CSI-2 specification defines the packet data size constraints for each data type.

When operating with relatively low DPHY line rates, e.g. below 400 Mbps, the MIPI CSI-2 receiver may not produce a video output. If this is observed, it may be resolved by increasing the TCLK-POST or THS-TRAIL values on your CSI-2 source.

The MIPI CSI-2 transmitter operating in passthrough may prevent the transmitter from producing an output on the DPHY interface when running on hardware.

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