1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

5.5. XGMII Signals

Table 19.  XGMII Signals
Signal Name Direction Width Description PHY Configurations
XGMII Transmit
xgmii_tx_control Input 4 TX control from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. 10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_tx_data Input 32 TX data from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.
xgmii_tx_valid Output 1 Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as shown below:
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
xgmii_tx_latency Output 16/24 (USXGMII) TX XGMII datapath latency for IEEE 1588, measured from XGMII user interface to PCS-PMA interface.
  • [15:10] Number of clock cycle
  • [9:0] Fractional number of clock cycle
Note: Only available when IEEE 1588 is enabled.
10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE I588
XGMII Receive
xgmii_rx_control Output 4 RX control to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. 10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_rx_data Output 32 RX data to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.
xgmii_rx_valid Output 1 Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table below.
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
 
xgmii_rx_latency Output 16/24 (USXGMII) RX XGMII datapath latency for IEEE 1588, measured from PCS-PMA interface to XGMII user interface.
  • [15:10] Number of clock cycle
  • [9:0] Fractional number of clock cycle
Note: Only available when IEEE 1588 is enabled.
10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE I588