1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

3.4. Operation Speed Switching

Table 11.  Operating Speed Switching Methodology
PHY Configuration Speed Switch Methodology
2.5G
1G/2.5G

1G to 2.5G switching is not supported for 1G/2.5G MBGASE-T.

10M/100M/1G/2.5G

Switching between (10M/100M/1G) and (2.5G): Transceiver reconfiguration with manual speed switching via CSR reconfiguration block available external to the PHY. The PHY must be reset after speed switch.

Switching within (10M/100M/1G): Use SGMII AN or CSR configuration

Note: Switching between 10M/100M/1G and 2.5G is not supported.
10M/100M/1G/2.5G/5G/10G (USXGMII)

Manual speed switching via CSR available inside the PHY.

Table 12.  Supported Operating Speed
PHY Configuration Features 10M 100M 1G 2.5G 5G 10G
2.5G Protocol 1000BASE-X @ 2.5x
Transceiver Data Rate 3.125 Gbps
MAC Interface 16-bit GMII @ 156.25 MHz/8-bit GMII @ 312.5 MHz
1G/2.5G Protocol 1000BASE-X 1000BASE-X @ 2.5x
Transceiver Data Rate 1.25 Gbps 3.125 Gbps
MAC Interface 16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz 16-bit GMII @ 156.25 MHz/8-bit GMII @ 312.5 MHz
10M/100M/1G/2.5G Protocol SGMII

100x data replication

SGMII

10x data replication

1000BASE-X/SGMII 1000BASE-X @ 2.5x
Transceiver Data Rate 1.25 Gbps 1.25 Gbps 1.25 Gbps 3.125 Gbps
MAC Interface 16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz

Clock enable high 1/100 cycles

16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz

Clock enable high 1/10 cycles

16-bit GMII @ 62.5 MHz/8-bit GMII @ 125 MHz

Clock enable always high

16-bit GMII @ 156.25 MHz/8-bit GMII @ 312.5 MHz

Clock enable always high

10M/100M/1G/2.5G/5G/10G (USXGMII) Protocol 10GBASE-R

1000x data replication

10GBASE-R

100x data replication

10GBASE-R

10x data replication

10GBASE-R

4x data replication

10GBASE-R

2x data replication

10GBASE-R

No data replication

Transceiver Data Rate 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps
MAC Interface 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal 32-bit XGMII @ 312.5 MHz with data valid signal