1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

5.7. PHY Status Signals

Table 21.  PHY Status Signals
Signal Name Direction Width Description PHY Configurations
led_char_err Output 1 Asserted when a 10-bit character error is detected for 1Gb or 2.5G.
  • 2.5G (MGBASE-T)
  • 1G/2.5G (MGBASE-T)
  • 10M/100M/1G/2.5G (MGBASE-T)
led_link Output 1 Asserted when the link synchronization for 1Gb or 2.5G is successful.
led_disp_err Output 1 Asserted when a 10-bit running disparity error is detected for 1Gb or 2.5G.
led_an Output 1 Asserted when auto-negotiation is completed.
  • 2.5G (MGBASE-T)
  • 1G/2.5G (MGBASE-T)
  • 10M/100M/1G/2.5G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
led_panel_link Output 1 When asserted, this signal indicates the following behavior:
Mode Behavior
1000 Base-X without auto-negotiation When asserted, indicates successful link synchronization.
SGMII mode without auto-negotiation When asserted, indicates successful link synchronization.
1000 Base-X with auto-negotiation Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
SGMII mode with MAC mode auto-negotiation Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
This signal is applicable only when SGMII 10M/100M mode is enabled.
  • 2.5G (MGBASE-T)
  • 1G/2.5G (MGBASE-T)
  • 10M/100M/1G/2.5G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
rx_block_lock Output 1 Asserted when the link synchronization for 10G of MGBASE-T and all speeds of USXGMII is successful.
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
tx_ready Output 1 Active high signal. When asserted, indicates that the TX datapath is ready to transmit data.
  • MGBASE-T
rx_ready Output 1 Active high signal. When asserted, indicates that the RX datapath is ready to receive data.
  • MGBASE-T
mrphy_pll_lock Output 1 Active high signal. When asserted, indicates that the PLL instantiated in the soft logic is locked to reference.
  • MGBASE-T (8-bit only)
o_tx_lanes_stable Output 1 Active-high asynchronous status signal for the TX datapath. Asserts when the TX datapath is ready to send data. Deasserts when the i_tx_rst_n or i_rst_n signal asserts.
  • USXGMII
o_rx_pcs_ready Output 1 Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when the i_rx_rst_n or i_rst_n signal asserts.
  • USXGMII
o_tx_pll_locked Output 1 Indicates that the TX serdes PLLs are locked.
  • USXGMII