1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

3.2.2. Reset Sequence

Figure 10. MGBASE-T Reset Block Diagram
Figure 11. MGBASE-T Reset Sequence (8-bit Option)
The following describes the reset sequence for MGBASE-T (8-bit) as shown in the figure above:
  • i_rst_n and o_rst_ack_n pair follows a handshake flow as shown in the figure above. i_tx_rst_n and o_tx_ack_n pair, and i_rx_rst_n and o_rx_ack_n pair follow the same flow for TX and RX paths respectively.
  • tx_ready is asserted by the IP several cycles after the i_rst_n is de-asserted. The assertion of tx_ready causes PLL to come out of reset and locked to reference. Locking is signalled by mrphy_pll_lock as shown in the MGBASE-T Reset Sequence (8-bit Option).
  • reset, tx_digitalreset and rx_digitalreset can be asserted at any point. After the mrphy_pll_lock is asserted, you can deassert reset, tx_digitalreset and rx_digitalreset to reset all soft logic.
Figure 12. MGBASE-T Reset Sequence (16-bit Option)
The following describes the reset sequence for MGBASE-T (16-bit) as shown in the figure above:
  • i_rst_n and o_rst_ack_n pair follows a handshake flow as shown in the figure above. i_tx_rst_n and o_tx_ack_n pair, and i_rx_rst_n and o_rx_ack_n pair follow the same flow for TX and RX paths respectively.
  • reset, tx_digitalreset and rx_digitalreset can be asserted at any point. Once tx_ready and rx_ready is asserted, you can deassert reset, tx_digitalreset and rx_digitalreset to reset all soft logic.
  • When the soft logic PLL is locked (mrphy_pll_lock is asserted) or when the rx_ready goes low, rx_digitalreset should be applied.
Figure 13. NBASE-T Reset Block Diagram
Figure 14. NBASE-T Reset Sequence
The following steps describe the reset sequence for NBASE-T as shown in the figure above:
  1. Drive the i_rst_n reset signal high while i_tx_rst_n and i_rx_rst_n reset signals are already deasserted.
  2. The o_rst_ack_n reset signal deasserts. This indicates that the IP core is no longer in the full reset.
    Note: This step doesn't indicate that the IP core is in fully functional state.
    Note: The o_tx_rst_ack_n and o_rx_rst_ack_n reset signals also deassert. The exact sequence and timing is not guaranteed.
  3. The IP core is fully out of reset. Assert o_tx_lanes_stable and o_rx_pcs_ready to indicate that the TX and RX datapaths are ready for use.
  4. Assert the i_tx_rst_n reset signal.
  5. The o_tx_lanes_stable signal deasserts to indicate that the TX datapath is no longer operational.
  6. The o_tx_rst_ack_n signal asserts indicating that the TX datapath is fully in reset. Then, deassert the i_tx_rst_n signal to bring the TX datapath out of the reset.
  7. Assert the i_rx_rst_n reset signal.
  8. The o_rx_pcs_ready signal deasserts to indicate that the RX datapath is no longer operational.
  9. The o_rx_rst_ack_n signal asserts indicating that the RX datapath is fully in reset. Then, deassert the i_rx_rst_n signal to bring the RX datapath out of the reset.
  10. Assert the i_rst_n reset signal.
  11. The o_tx_lanes_stable and o_rx_pcs_ready signals deassert to indicate that TX and RX datapath are no longer operational.
  12. The o_rst_ack_n signals assert to indicate the IP core is fully in reset. To bring the IP core out of the reset, deassert the i_rst_n reset signal.
  13. Assert tx_digital_reset once the tx_lane_stable assert.
  14. Assert rx_digital_reset once the rx_pcs_ready assert.

System Considerations

  • During the reset, hold the i_reconfig_reset signal asserted for several valid reconfiguration clock cycles to ensure the Avalon® memory-mapped interface and soft CSRs are fully reset.
  • Access to any Avalon® memory-mapped interface is available while the i_reconfig_reset signal is low.