1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

3.3. Timing Constraints

Table 10.  Timing Constraints
PHY Configuration Constrain PHY for
2.5G (MGBASE-T) 2.5G datapath
1G/2.5G (MGBASE-T) 2.5G datapath
10M/100M/1G/2.5G/5G/10G (USXGMII) 10G datapath
10M/100M/1G/2.5G (MGBASE-T, SGMII) 2.5G datapath
Apply the following constraints to the .sdc files when you enable the ENABLE_GMII_ADAPTER parameter:
set_clock_groups -logically_exclusive -group [get_clocks "*|iopll_tx_outclk0"] -group [get_clocks "*|iopll_tx_outclk3"] 

set_clock_groups -logically_exclusive -group [get_clocks "*|iopll_tx_outclk0"] -group [get_clocks "*|iopll_tx_outclk2"]  

set_clock_groups -logically_exclusive -group [get_clocks "*|iopll_tx_outclk2"] -group [get_clocks "*|iopll_tx_outclk3"] 

create_clock -name {csr_clk} -period 10.000 (note: period should be as per actual clock used) 
set_clock_groups -exclusive -group csr_clk 

create_clock -name {gmii8b_tx_clkin} -period 8.000 ( note: for 2.5G replace 8.00ns with 3.2ns)  
set_clock_groups -logically_exclusive -group [get_clocks {gmii8b_tx_clkin}] -group [get_clocks {intel_mge_phy_0|iopll_tx_outclk2}]
 
set_clock_groups -logically_exclusive -group [get_clocks {gmii8b_tx_clkin}] -group [get_clocks {intel_mge_phy_0|iopll_tx_outclk3}] 

 set_clock_groups -logically_exclusive -group [get_clocks {gmii8b_tx_clkin}] -group [get_clocks {intel_mge_phy_0|iopll_tx_outclk0}]