1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

5.10. GTS Reset Sequencer Signals

Table 24.  GTS Reset Sequencer Signals
Signal Name Direction Width Description PHY Configurations
o_src_rs_req Output 1 Request signal to GTS Reset Sequencer. All
i_src_rs_grant Input 1 Grant signal from GTS Reset Sequencer. All