1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

2.6.1. Adding the Agilex™ 5 Reference and System PLL IP

Figure 5.  1G/2.5G/5G/10G Multirate Ethernet PHY Interface with Agilex™ 5 Reference and System PLL Clocks IP

You must connect the Agilex™ 5 Reference and System PLL Clocks Intel® FPGA IP to the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP to compile the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP successfully.

The Agilex™ 5Reference and System PLL Clock Intel® FPGA IP configures the reference and system clocks of the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP