1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

3.1. Architecture

Figure 6. Architecture of the 2.5G, 1G/2.5G, 10M/100M/1G/2.5G (MGBASE-T) Configuration
  • The MGBASE-T configuration for Agilex™ 5 devices supports the following variants:
    • 2.5G
    • 1G/2.5G
    • 10M/100M/1G/2.5G
  • The MGBASE-T configuration is clocked at 156.25 MHz to achieve a maximum data rate of 2.5G.
  • The MGBASE-T configuration includes the following interfaces:
    • 10M/100M—MII, 4 bit
    • 1G/2.5G—GMII, 8 bit or 16 bit
    • 10M/100M/1G/2.5G—GMII, 8 bit or 16 bit
  • The MGBASE-T configuration supports the following line rates:
    • 1.25 Gbps for 10M/100M/1G
    • 3.125 Gbps for 2.5G
  • The MGBASE-T configuration uses PMA direct mode.
  • The 1G/2.5G MGBASE-T configuration mode supports IEEE 1588v2 feature.
  • GMII 8-bit adapter is used with HPS EMAC configuration along with the MGBASE-T mode.
Figure 7. Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
  • The NBASE-T/USXGMII configuration for Agilex™ 5 devices supports 10M/100M/1G/2.5G/5G/10G variant.
  • The NBASE-T/USXGMII configuration is clocked at 312.5 MHz to achieve a maximum data rate of 10G.
  • The NBASE-T/USXGMII configuration includes the following interfaces:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
  • The NBASE-T/USXGMII configuration supports the following line rates:
    • 10 Gbps for all USXGMII data rates
  • The NBASE-T/USXGMII configuration uses PCS direct mode.
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