1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Architecture 3.2. Clocking and Reset Sequence 3.3. Timing Constraints 3.4. Operation Speed Switching 3.5. USXGMII 3.6. Fmax Requirement
3.2. Clocking and Reset Sequence x
3.2.1. Clocking 3.2.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

2.2.1. Intel® FPGA IP Evaluation Mode

The free Intel® FPGA IP Evaluation Mode allows you to evaluate licensed Intel® FPGA IP in simulation and hardware before purchase. Intel® FPGA IP Evaluation Mode supports the following evaluations without additional license:
  • Simulate the behavior of a licensed Intel® FPGA IP in your system.
  • Verify the functionality, size, and speed of the IP quickly and easily.
  • Generate time-limited device programming files for designs that include IPs.
  • Program a device with your IP and verify your design in hardware.

Intel® FPGA IP Evaluation Mode supports the following operation modes:

  • Tethered—Allows running the design containing the licensed Intel® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial JTAG cable connected between the JTAG port on your board and the host computer, which is running the Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Quartus® Prime software, and requires no Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IPs in the design support tethered mode, the evaluation time runs until any IP evaluation expires. If all of the IPs support unlimited evaluation time, the device does not time-out.
  • Untethered—Allows running the design containing the licensed IP for a limited time. The IP reverts to untethered mode if the device disconnects from the host computer running the Quartus® Prime software. The IP also reverts to untethered mode if any other licensed IP in the design does not support tethered mode.

When the evaluation time expires for any licensed Intel® FPGA IP in the design, the design stops functioning. All IPs that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP for production, purchase a full production license for the IP.

You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.

Figure 3.  Intel® FPGA IP Evaluation Mode Flow
Note: Refer to each IP's user guide for parameterization steps and implementation details.

Altera licenses IPs on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IPs that require a production license, before generating programming files that you may use for an unlimited time. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Intel® FPGA Self-Service Licensing Center.

The Intel® FPGA Software License Agreements govern the installation and use of licensed IPs, the Quartus® Prime design software, and all unlicensed IPs.

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