1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 7/08/2024
Public
Document Table of Contents

5.6. GMII Signals

Table 20.  GMII Signals
Signal Name Direction Width Description PHY Configurations
TX GMII signals (16-bit)
gmii16b_tx_d Input 16 TX data from the MAC for 1G and 2.5G.
  • 2.5G (MGBASE-T)
  • 1G/2.5G (MGBASE-T)
  • 10M/100M/1G/2.5G (MGBASE-T)
gmii16b_tx_en Input 2 TX valid from the MAC for 1G and 2.5G.
gmii16b_tx_err Input 2 TX error from MAC for 1G and 2.5G.
tx_clkena Output 1 TX clock enable for SGMII 10M/100M operating speeds.
  • 10M/100M/1G/2.5G (MGBASE-T)
gmii16b_tx_latency Output 22 The latency of the PHY excluding the PMA block on the TX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.
This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.
Note: This is the latency output when ENABLE_ADAPTER is 1. The final latency value takes this value and multiply with the serial rate and divide by 20 clock period.
  • 2.5G
  • 1G/2.5G with IEEE 1588v2 feature
RX GMII signals (16-bit)
gmii16b_rx_d Output 16 RX data to the MAC for 1G and 2.5G.
  • 10M/100M/1G/2.5G (MGBASE-T)
gmii16b_rx_err Output 2 RX error to MAC for 1G and 2.5G.
gmii16b_rx_dv Output 2 RX valid to MAC for 1G and 2.5G.
rx_clkena Output 1 RX clock enable for SGMII 10M/100M operating speeds.
gmii16b_rx_latency Output 22 The latency of the PHY excluding the PMA block on the RX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.
This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.
Note: This is the latency output when ENABLE_ADAPTER is 1. The final latency value takes this value and multiply with the serial rate and divide by 20 clock period.
  • 2.5G
  • 1G/2.5G with IEEE 1588v2 feature
TX GMII signals (8-bit)
gmii8b_tx_clkin Input 1 Input clock for GMII (8-bit).
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G(MGBASE-T)
gmii8b_tx_clkout Output 2 GMII TX clock, derived from tx_pll_refclk. Provides 312.5 MHz timing reference for 2.5G; 125 MHz for 1G, 100M, and 10M.
gmii8b_tx_rst_n Input 1 Reset signal for the GMII8B adapter on the TX path.
gmii8b_mac_tx_d Input 8 TX data from MAC for 1G and 2.5G.
gmii8b_mac_txen Input 1 TX valid from MAC for 1G and 2.5G.
gmii8b_mac_txer Input 1 TX error from MAC for 1G and 2.5G.
RX GMII signals (8-bit)
gmii8b_rx_clkout Output 1 GMII RX clock, derived from tx_pll_refclk. Provides 312.5 MHz timing reference for 2.5G; 125 MHz for 1G, 100M, and 10M.
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G(MGBASE-T)
gmii8b_rx_rst_n Input 1 Reset signal for the GMII8B adapter on the RX path.
gmii8b_mac_rxd Output 8 RX data to MAC for 1G and 2.5G.
gmii8b_mac_rxdv Output 1 RX valid to MAC for 1G and 2.5G.
gmii8b_mac_rxer Output 1 RX error to MAC for 1G and 2.5G.
gmii8b_mac_col Output 1 GMII/MII collision detection to MAC.
gmii8b_mac_crs Output 1 GMII/MII carrier sense detection to MAC.
gmii8b_mac_speed Input 2 MAC speed indication.